 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| q-smint ? ix 2b1 q s econd gen. m odular i sdn nt (i ntelligent e x tended) pef 81912/81913 version 1.3 data sheet, ds 1, march 2001 wired communications never stop thinking.
edition march 2001 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications q-smint ? ix 2b1 q s econd gen. m odular i sdn nt (i ntelligent e x tended) pef 81912/81913 version 1.3 data sheet, ds 1, march 2001 never stop thinking. pef 81912/81913 revision history: march 2001 ds 1 previous version: preliminary data sheet 10.00 page subjects (major changes since last revision) all editorial changes, addition of notes for clarification etc. table 1 , chapter 1.3 introduced new versions 81913 with extended performance of the u-interface chapter 2.1.1.1 sci: header description: added to sequences 43 h , 41 h and 49 h : generally, it can be used for any register access to the address range 00 h -7d h . chapter 2.3.2 iom-2 handler: removed u-transceiver (u) from listing of functional units with programmable time slot and data port. figure 12 figure data access via cdax0 and cdax1 register pairs corrected: input swap has influence on the input enable (en_i0,1), too chapter 2.5.5.2 c/i commands: removed unconditional command from description c/i-command dr chapter 2.5.5.3 lt-s state machine: c/i=command ail removed (no valid input to the lt-s state machine) chapter 2.6.2.1 hdlc: removed from description rbc: (bytes, which are ready for next read access) and (blocks, which have been already read). chapter 2.6.3.1 hdlc: possible error conditions: added behavioral description in case of an xpr interrupt chapter 4 detailed register description: ? u-transceiver mode evaluation timing: clarified description ? register id: reset value of version 1.3 is 01 h (not 00 h ) ? rsta.sa1,0: clarified note ? cix1.codx1: bits 5-0 of c/i-channel 1 (not 7-2) ? iom_cr:tic_dis: added for clarification: this means that the timeslots tic, a/ b, s/g and bac are not available any more. chapter 5.1 absolute maximum ratings: maximum voltage on vdd: 4.2v (before: 4.6v) chapter 5.1 refined references for esd requirements: ...(cdm), eia/jesd22-a114b (hbm) --- chapter 5.2 input/output leakage current set to 10a (before: 1a) table 43 u-transceiver characteristics: enhanced s/n+d for 81913 and threshold level for 81912 and 81913 distinguished for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 81912/81913 revision history: march 2001 ds 1 previous version: preliminary data sheet 10.00 page subjects (major changes since last revision) chapter 5.6.2 chapter 5.6.3 ac-timing sci/parallel c interface: enhanced timing specifications chapter 5.6.3 added restriction for control interval t ri chapter 5.6.5 parameters of the uvd/por circuit: defined reduced range of hysteresis: min. 30mv/max. 90mv relaxed upper limit of detection threshold to 2.92v (before: 2.9v) defined max. rising vdd for power-on chapter 7.2.5 register summary u-transceiver 4b3t: reset value of masku is ff h (not 00 h ) chapter 7.3 external circuitry for t-smint updated pef 81912/81913 table of contents page data sheet 2001-03-30 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 features pef 81912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 features pef 81913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 not supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 different are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.8 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.8.1 specific pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.9 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 microcontroller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.1 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1.1.1 programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.2 parallel microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.3 microcontroller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 iom -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.1 iom -2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.2 iom -2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.2.1 controller data access (cda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.2.2 serial data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.3 iom -2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.3.1 handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3.3.2 error treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.3.3.3 monitor channel programming as a master device . . . . . . . . . . . 48 2.3.3.4 monitor channel programming as a slave device . . . . . . . . . . . . 48 2.3.3.5 monitor time-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3.3.6 monitor interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3.4 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3.5 d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.5.1 application example for d-channel access control . . . . . . . . . . . . . 52 2.3.5.2 tic bus handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.5.3 stop/go bit handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.3.5.4 d-channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.5.5 state machine of the d-channel arbiter . . . . . . . . . . . . . . . . . . . . . . 55 2.3.6 activation/deactivation of iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . 58 2.4 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.4.1 2b1q frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.4.2 maintenance channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.2.1 reporting to the c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 pef 81912/81913 table of contents page data sheet 2001-03-30 2.4.2.2 access from the c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.2.3 availability of maintenance channel information . . . . . . . . . . . . . . . . 64 2.4.2.4 m-bit register access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.3 processing of the eoc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.3.1 eoc commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.3.2 eoc processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.3.3 eoc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4.3.4 examples for different eoc modes . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.4 processing of the overhead bits m4, m5, m6 . . . . . . . . . . . . . . . . . . . . 74 2.4.4.1 m4 bit reporting to the c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.2 m4 bit reporting to state machine . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.3 m5, m6 bit reporting to the c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.4 summary of m4, m5, m6 bit reporting . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.5 m4, m5, m6 bit control mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.6 cyclic redundancy check / febe bit . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4.7 block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.7.1 near-end and far-end block error counter . . . . . . . . . . . . . . . . . . . 80 2.4.7.2 testing block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.8 scrambling/ descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.9 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.10 state machines for line activation / deactivation . . . . . . . . . . . . . . . . . 84 2.4.10.1 notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4.10.2 standard nt state machine (iec-q / ntc-q compatible) . . . . . . . . 86 2.4.10.3 inputs to the u-transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.4.10.4 outputs of the u-transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.4.10.5 description of the nt-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.10.6 simplified nt state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.11 metallic loop termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.12 u-transceiver interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.5 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.5.1 line coding, frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.5.2 s/q channels, multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.5.3 data transfer between iom?-2 and s0 . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.4 loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.5 control of s-transceiver / state machine . . . . . . . . . . . . . . . . . . . . . . 105 2.5.5.1 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.5.5.2 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.5.5.3 state machine lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.6 s-transceiver enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.5.7 interrupt structure s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.6 hdlc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.6.1 message transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pef 81912/81913 table of contents page data sheet 2001-03-30 2.6.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.6.2.1 structure and control of the receive fifo . . . . . . . . . . . . . . . . . . . 120 2.6.2.2 receive frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.6.3 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.6.3.1 structure and control of the transmit fifo . . . . . . . . . . . . . . . . . . 128 2.6.3.2 transmit frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 2.6.4 access to iom -2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 2.6.5 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 2.6.6 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 2.6.7 hdlc controller interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 2.6.8 test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 2.6.9 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.1 layer 1 activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.1.1 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . 139 3.1.2 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.1.3 complete activation initiated by nt . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.1.4 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 3.1.5 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.2 layer 1 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 3.2.1 analog loopback u-transceiver (no. 3) . . . . . . . . . . . . . . . . . . . . . . . 144 3.2.2 analog loop-back s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 3.2.3 loopback no.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.2.3.1 complete loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.2.3.2 loopback no.2 - single channel loopbacks . . . . . . . . . . . . . . . . . . 147 3.2.4 local loopbacks featured by the loop register . . . . . . . . . . . . . . . 147 3.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . 149 3.3.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.3.3 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.3.4 oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 3.3.5 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.1 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.4 reset of u-transceiver functions during deactivation or with c/i-code reset 166 4.5 u-transceiver mode register evaluation timing . . . . . . . . . . . . . . . . . . 167 4.6 detailed hdlc control and c/i registers . . . . . . . . . . . . . . . . . . . . . . . . 168 4.6.1 rfifo - receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 pef 81912/81913 table of contents page data sheet 2001-03-30 4.6.2 xfifo - transmit fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.6.3 istah - interrupt status register hdlc . . . . . . . . . . . . . . . . . . . . . . . 169 4.6.4 maskh - mask register hdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.6.5 star - status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.6.6 cmdr - command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.6.7 modeh - mode register hdlc controller . . . . . . . . . . . . . . . . . . . . . 174 4.6.8 exmr - extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.6.9 timr - timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.6.10 sap1 - sapi1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.6.11 sap2 - sapi2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.6.12 rbcl - receive frame byte count low . . . . . . . . . . . . . . . . . . . . . . . 179 4.6.13 rbch - receive frame byte count high for d-channel . . . . . . . . . . 179 4.6.14 tei1 - tei1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.6.15 tei2 - tei2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.6.16 rsta - receive status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.6.17 tmh -test mode register hdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.6.18 cir0 - command/indication receive 0 . . . . . . . . . . . . . . . . . . . . . . . . 183 4.6.19 cix0 - command/indication transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . 184 4.6.20 cir1 - command/indication receive 1 . . . . . . . . . . . . . . . . . . . . . . . . 185 4.6.21 cix1 - command/indication transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . 186 4.7 detailed s-transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.7.1 s_conf0 - s-transceiver configuration register 0 . . . . . . . . . . . . . . 186 4.7.2 s_conf2 - s-transmitter configuration register 2 . . . . . . . . . . . . . . 188 4.7.3 s_sta - s-transceiver status register . . . . . . . . . . . . . . . . . . . . . . . 188 4.7.4 s_cmd - s-transceiver command register . . . . . . . . . . . . . . . . . . . . 189 4.7.5 sqrr - s/q-channel receive register . . . . . . . . . . . . . . . . . . . . . . . 190 4.7.6 sqxr- s/q-channel transmit register . . . . . . . . . . . . . . . . . . . . . . . 191 4.7.7 istas - interrupt status register s-transceiver . . . . . . . . . . . . . . . . . 191 4.7.8 masks - mask s-transceiver interrupt . . . . . . . . . . . . . . . . . . . . . . . . 192 4.7.9 s_mode - s-transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.8 interrupt and general configuration registers . . . . . . . . . . . . . . . . . . . . 194 4.8.1 ista - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 4.8.2 mask - mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.8.3 mode1 - mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.8.4 mode2 - mode2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 4.8.5 id - identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.8.6 sres - software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.9 detailed iom ? -2 handler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.9.1 cdaxy - controller data access register xy . . . . . . . . . . . . . . . . . . . . 199 4.9.2 xxx_tsdpxy - time slot and data port selection for chxy . . . . . . . 200 4.9.3 cdax_cr - control register controller data access ch1x . . . . . . . . 201 4.9.4 s_cr - control register s-transceiver data . . . . . . . . . . . . . . . . . . . 202 pef 81912/81913 table of contents page data sheet 2001-03-30 4.9.5 hci_cr - control register for hdlc and ci1 data . . . . . . . . . . . . . . 204 4.9.6 mon_cr - control register monitor data . . . . . . . . . . . . . . . . . . . . . 205 4.9.7 sds1_cr - control register serial data strobe 1 . . . . . . . . . . . . . . . 206 4.9.8 sds2_cr - control register serial data strobe 2 . . . . . . . . . . . . . . . 207 4.9.9 iom_cr - control register iom data . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.9.10 mcda - monitoring cda bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.9.11 sti - synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.9.12 asti - acknowledge synchronous transfer interrupt . . . . . . . . . . . . . 210 4.9.13 msti - mask synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . 210 4.10 detailed monitor handler registers . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.10.1 mor - monitor receive channel . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.10.2 mox - monitor transmit channel . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.10.3 mosr - monitor interrupt status register . . . . . . . . . . . . . . . . . . . 212 4.10.4 mocr - monitor control register . . . . . . . . . . . . . . . . . . . . . . . . . . 212 4.10.5 msta - monitor status register . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.10.6 mconf - monitor configuration register . . . . . . . . . . . . . . . . . . . . 214 4.11 detailed u-transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.11.1 opmode - operation mode register . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.11.2 mfilt - m bit filter options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.11.3 eocr - eoc read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 4.11.4 eocw - eoc write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 4.11.5 m4rmask - m4 read mask register . . . . . . . . . . . . . . . . . . . . . . . . . 218 4.11.6 m4wmask - m4 write mask register . . . . . . . . . . . . . . . . . . . . . . . . . 218 4.11.7 m4r - m4 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 4.11.8 m4w - m4 write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 4.11.9 m56r - m56 read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.11.10 m56w - m56 write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.11.11 ucir - c/i code read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.11.12 uciw - c/i code write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 4.11.13 test - test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 4.11.14 loop - loop back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 4.11.15 febe - far end block error counter register . . . . . . . . . . . . . . . . . . 225 4.11.16 nebe - near end block error counter register . . . . . . . . . . . . . . . . . 226 4.11.17 istau - interrupt status register u-interface . . . . . . . . . . . . . . . . . . . 226 4.11.18 masku - mask register u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . 227 4.11.19 fw_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.5 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 pef 81912/81913 table of contents page data sheet 2001-03-30 5.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.6.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.6.2 serial p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.6.3 parallel p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 5.6.5 undervoltage detection characteristics . . . . . . . . . . . . . . . . . . . . . . . 241 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7 appendix: differences between q- and t-smint?ix . . . . . . . . . . . . . . 245 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.2.1 u-interface conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.2.2 u-transceiver state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.2.3 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 7.2.4 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.2.5 register summary u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 7.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 8 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 pef 81912/81913 list of figures page data sheet 2001-03-30 figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3 application example q-smint ? ix: low cost intelligent nt . . . . . . . . 14 figure 4 control via p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5 control via iom?-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 serial command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 direct/indirect register address mode . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9 reset generation of the q-smint ? ix . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10 iom -2 frame structure of the q-smint ? ix . . . . . . . . . . . . . . . . . . . 28 figure 11 architecture of the iom?-2 handler. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12 data access via cdax0 and cdax1 register pairs . . . . . . . . . . . . . . . 32 figure 13 examples for data access via cdaxy registers . . . . . . . . . . . . . . . . . 33 figure 14 data access when looping tsa from du to dd . . . . . . . . . . . . . . . . . 34 figure 15 data access when shifting tsa to tsb on du (dd) . . . . . . . . . . . . . . 35 figure 16 example for monitoring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17 interrupt structure of the synchronous data transfer . . . . . . . . . . . . . 39 figure 18 examples for the synchronous transfer interrupt control with one stixy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19 data strobe signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 20 monitor channel protocol (iom?-2) . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21 monitor channel, transmission abort requested by the receiver. . . . 47 figure 22 monitor channel, transmission abort requested by the transmitter. . 47 figure 23 monitor channel, normal end of transmission . . . . . . . . . . . . . . . . . . 47 figure 24 monitor interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25 cic interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 26 d-channel arbitration: m c has no hdlc and no direct access to tic bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 27 structure of last octet of ch2 on du . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 28 structure of last octet of ch2 on dd . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 29 state machine of the d-channel arbiter (simplified view). . . . . . . . . . 56 figure 30 deactivation of the iom ? -2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 31 u-superframe structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 32 u-basic frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 33 u2b1q framer - data flow scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 34 u2b1q deframer - data flow scheme . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 35 write access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 36 read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 37 eoc message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 38 eoc command/message transmission . . . . . . . . . . . . . . . . . . . . . . . 69 figure 39 maintenance channel filtering options . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 40 m4 bit report timing (statemachine vs. c). . . . . . . . . . . . . . . . . . . . 75 pef 81912/81913 list of figures page data sheet 2001-03-30 figure 41 m4, m5, m6 bit control in receive direction . . . . . . . . . . . . . . . . . . . . 77 figure 42 m4, m5, m6 bit control in transmit direction . . . . . . . . . . . . . . . . . . . 77 figure 43 crc-process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 44 block error counter test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 45 explanation of state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 46 standard nt state machine (iec-q / ntc-q compatible) (footnotes: see dependence of outputs on page 91 ) . . . . . . . . . 86 figure 47 simplified nt state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 48 pulse streams selecting quiet mode . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 49 interrupt structure u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 50 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 51 frame structure at reference points s and t (itu i.430). . . . . . . . . 103 figure 52 s-transceiver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 53 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 54 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 55 state machine lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 56 interrupt structure s-transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 57 rfifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 58 data reception procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 59 reception sequence example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 60 receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 61 data transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 62 transmission sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 63 transmit data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 64 timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 65 interrupt status registers of the hdlc controller . . . . . . . . . . . . . . . 137 figure 66 layer 2 test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 67 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . 139 figure 68 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 69 complete activation initiated by q-smint ? ix. . . . . . . . . . . . . . . . . . 141 figure 70 complete deactivation initiated by exchange . . . . . . . . . . . . . . . . . . 142 figure 71 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 72 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 73 external loop at the s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 74 complete loopback options in nt-mode . . . . . . . . . . . . . . . . . . . . . 146 figure 75 loopbacks featured by register loop . . . . . . . . . . . . . . . . . . . . . . 148 figure 76 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 77 external circuitry u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 78 external circuitry s-interface transmitter . . . . . . . . . . . . . . . . . . . . . 152 figure 79 external circuitry s-interface receiver . . . . . . . . . . . . . . . . . . . . . . . 153 figure 80 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 81 address space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 pef 81912/81913 list of figures page data sheet 2001-03-30 figure 82 q-smint ? ix interrupt status registers . . . . . . . . . . . . . . . . . . . . . . 156 figure 83 maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . 233 figure 84 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 85 iom?-2 interface - bit synchronization timing . . . . . . . . . . . . . . . . . 234 figure 86 iom ? -2 interface - frame synchronization timing . . . . . . . . . . . . . . 234 figure 87 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 figure 88 microprocessor read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 89 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 90 multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 91 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 92 microprocessor read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 93 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 94 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 95 reset input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 96 undervoltage control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 97 intc-q compatible state machine q-smint ? ix: 2b1q . . . . . . . . . 247 figure 98 simplified state machine q-smint ? ix: 2b1q . . . . . . . . . . . . . . . . . 248 figure 99 iec-t/ntc-t compatible state machine t-smint?ix: 4b3t . . . . . . 249 figure 100 interrupt structure u-transceiver q-smint ? ix: 2b1q . . . . . . . . . . . 251 figure 101 interrupt structure u-transceiver t-smint?ix: 4b3t . . . . . . . . . . . . 252 figure 102 external circuitry q- and t-smint?ix . . . . . . . . . . . . . . . . . . . . . . . . 256 pef 81912/81913 list of tables page data sheet 2001-03-30 table 1 nt products of the 2nd generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2 hdlc naming convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 interface selection for the q-smint ? ix . . . . . . . . . . . . . . . . . . . . . . . 17 table 6 header byte code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7 bus operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 mclk frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9 reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10 examples for synchronous transfer interrupts . . . . . . . . . . . . . . . . . . 38 table 11 transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12 receive direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13 q-smint ? ix configuration settings in intelligent nt applications . . . 55 table 14 major differences d-channel arbiter intc-q and q-smint ? ix. . . . . 56 table 15 u-superframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 16 enabling the maintenance channel (receive direction) . . . . . . . . . . . 64 table 17 coding of eoc-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 18 usage of supported eoc-commands. . . . . . . . . . . . . . . . . . . . . . . . . 67 table 19 eoc auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 20 transparent mode 6 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 21 transparent mode @change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 22 transparent mode tll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 23 u - transceiver c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 24 timers used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 25 u-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 26 signal output on uk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 27 c/i-code output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 28 changes to achieve simplified nt state machine . . . . . . . . . . . . . . . . 95 table 29 appearance of the state machine to the software . . . . . . . . . . . . . . . 98 table 30 ansi maintenance controller states . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 31 s/q-bit position identification and multi-frame structure . . . . . . . . . 104 table 32 receive byte count with rbc11...0 in the rbch and rbcl registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 33 receive information at rme interrupt . . . . . . . . . . . . . . . . . . . . . . . . 128 table 34 xpr interrupt (availability of the xfifo) after xtf, xme commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 35 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 36 u-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 37 s-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 38 crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 39 reset of u-transceiver functions during deactivation or with c/i-code reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 pef 81912/81913 list of tables page data sheet 2001-03-30 table 41 maximum input currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 42 s-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 43 u-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 44 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 45 reset input signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 46 parameters of the uvd/por circuit . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 47 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 48 related documents to the u-interface. . . . . . . . . . . . . . . . . . . . . . . . 246 table 49 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 50 dimensions of external components. . . . . . . . . . . . . . . . . . . . . . . . . 257 pef 81912/81913 overview data sheet 1 2001-03-30 1 overview the pef 81912 / 81913 (q-smint ? ix) offers most features known from the peb / pef 8191 [12] and can hence replace the latter in its major applications. however, it does not replace the peb/pef 8191 in applications that use the s-transceiver in te mode. the q-smint ? ix features u-transceiver, s-transceiver, hdlc controller and an iom ? - 2 interface on a single chip. a microcontroller interface provides access to both transceivers, the hdlc controller as well as the iom ? -2 interface. main target applications of the q-smint ? ix are intelligent nt applications which require one single hdlc controller. table 1 summarizes the 2nd generation nt products. ? table 1 nt products of the 2nd generation pef80912 pef80913 PEF81912 pef81913 pef82912 pef82913 q-smint ? o q-smint ? ix q-smint ? i package p-mqfp-44 p-mqfp-64 p-tqfp-64 p-mqfp-64 p-tqfp-64 register access no u+s+hdlc+ iom ? -2 u+s+ iom ? -2 access via n.a. parallel (or sci or iom ? -2) parallel (or sci or iom ? -2) mclk, watchdog timer, sds, bcl, d- channel arbitration, iom ? -2 access and manipulation etc. provided no yes yes hdlc controller no yes no nt1 mode available yes (only) no no extended u- performance 20kft no yes no yes no yes pef 81912/81913 overview data sheet 2 2001-03-30 1.1 references [1] ts 102 080, transmission and multiplexing ; isdn basic rate access; digital transmission system on metallic local lines, etsi, november 1998 [2] t1.601-1998 (revision of ansi t1.601-1992), isdn-basic access interface for use on metallic loops for application on the network side of the nt (layer 1 specification), ansi, 1998 [3] st/laa/elr/dnp/822, cnet, france [4] rc7355e, 2b1q generic physical layer specification, british telecommunications plc., 1997 [5] fza ts 0095/01:1997-10, technische spezifikationen fr netzabschlu?ger?te fr den isdn basisanschlu? (nt-ba), post & telekom austria, 1997 [6] pr ets 300 012 draft, isdn; basic user network interface (uni), etsi, november 1996 [7] t1.605-1991, isdn-basic access interface for s and t reference points (layer 1 specification), ansi, 1991 [8] i.430, isdn user-network interfaces: layer 1 recommendations, itu, november 1988 [9] iec-q, isdn echocancellation circuit, peb 2091 v4.3, users manual 02.95, siemens ag, 1995 [10] sbcx, s/t bus interface circuit extended, peb 2081 v3.4, users manual 11.96, siemens ag, 1996 [11] ntc-q, network termination controller (2b1q), peb / pef 8091 v1.1, data sheet 10.97, siemens ag, 1997 [12] intc-q, intelligent network termination controller (2b1q), peb / pef 8191 v1.1, data sheet 10.97, siemens ag, 1997 [13] iom ? -2 interface reference guide, siemens ag, 03.91 [14] scout-s(x), siemens codec with s/t-transceiver, psb 2138x v1.3, preliminary data sheet 8.99, infineon technologies, 1999 [15] pita, pci interface for telephony/data applications v0.3, sican gmbh, september 1997 [16] dual channel slicofi-2, hv-slic; duslic; peb3265, 4265, 4266; data sheet ds2, infineon technologies, july 2000. ? pef 81912/81913 overview data sheet 3 2001-03-30 ? 2b1q second gen. modular isdn nt (intelligent extended) q-smint ? ix pef 81912/81913 version 1.3 type package pef 81912/81913 p-mqfp-64 pef 81912/81913 p-tqfp-64 1.2 features pef 81912 features known from the peb/pef 8191 ? u-transceiver, s-transceiver and hdlc controller on one chip ? perfectly suited for low-cost intelligent nts that require one single hdlc controller ? u-interface (2b1q) conform to etsi [1], ansi [2] and cnet [3]: C meets all transmission requirements on all etsi, ansi and cnet loops with margin C conform to british telecoms rc7355e [4] C compliant with etsi 10 ms micro interruptions C mlt input and decode logic (ansi [2]) ? s/t-interface conform to etsi [6], ansi [7] and itu [8] C supports point-to-point and bus configurations C meets and exceeds all transmission requirements ? activation status led supported ? bcl, sds1, sds2, programmable mclk, watchdog timer, ? access to iom ? -2 c/i and monitor channels ? power-down mode and reset states (e.g. s-transceiver) for individual circuits ? automatic d-channel arbitration between s-bus and local hdlc controller ? parallel or serial p-interface p-mqfp-64-1,-2 p-mqfp-64 p-tqfp-64-1 p-tqfp-64 pef 81912/81913 overview data sheet 4 2001-03-30 ? new features ? reduced number of external components for external u-hybrid required ? optional use of up to 2x20 w resistors on the line side of the transformer (e.g. ptcs) ? pin uref and the according external capacitor removed ? improved esd (2 kv instead of <850 v) ? inputs accept 3.3 v and 5 v ? i/o (open drain) accepts pull-up to 3.3 v 1) ? led signal is programmable but can also automatically indicate the activation status (mode select via 1 bit) ? pin compatible with t-smint ? ix (2nd generation) ? priority setting (8/10) for off-chip and on-chip hdlc controller ? improved fifo structure (scout) ? enhanced iom ? -2 timeslot access and manipulation (scout) ? hdlc extended transparent mode (scout) ? mclk can be disabled (scout) ? external awake (eaw ) ? optional: all registers can be read and written to via new monitor channel concept ? optional: implementation of s-transceiver statemachine in software ? indirect addressing (scout) ? hdlc access to b-channels, d-channel and any combination of them ? programmable strobes sds1/2 are more flexible, e.g. active during several timeslots ? power-on reset and undervoltage detection with no external components ? lowest power consumption due to: C low power cmos technology (0.35) C newly optimized low-power libraries C high output swing on u- and s-line interface leads to minimized power consumption C single 3.3 volt power supply ? 200 mw (intc-q: 295 mw) power consumption with random data over etsi loop 2 (external loads on the s and u interface only and no additional external loads). ? 15 mw typical power consumption in power down (intc-q: 28 mw) 1.3 features pef 81913 the q-smint ? ix pef 81913 provides all features of the pef 81912. additionally, a significantly enhanced performance of the u-interface as compared to etsi [1], ansi [2] and cnet [3] requirements is guaranteed: transparent transmission on 20kft awg26 with a ber < 10 -7 (without noise). 1) pull-ups to 5 v must be avoided. a so-called hot-electron-effect would lead to long term degradation. pef 81912/81913 overview data sheet 5 2001-03-30 1.4 not supported are ... ? integrated u-hybrid ? self test request and self test passed of u-transceiver ? te-mode of the s-transceiver ? dect-link capability ? sra (capacitive receiver coupling is not suited for s-feeding). ? nt-star with star point on the iom ? -2 bus (already not supported in intc-q). ? hdlc automode ? no access to s2-5 channels. access only to s1 and q channel as in scout. no selection between transparent and non-auto mode provided. ? the oscillator architecture was changed with respect to the intc-q to reduce power consumption. as a consequence, the q-smint ? ix always needs a crystal and pin xin can not be connected to an external clock as it was possible for iec-q and ntc- q. this does not limit the use of the q-smint ? ix in nts since all nt designs use crystals anyway. 1.5 different are ... ? hdlc naming convention of transparent modes has changed (as in scout). the according bit combination in the modeh register remains unchanged, hence software compatibility is ensured. table 2 hdlc naming convention old (icc/intc-q) new address comparison transparent 1 transparent 2 tei transparent 2 transparent 0 none transparent 3 transparent 1 sapi pef 81912/81913 overview data sheet 6 2001-03-30 1.6 pin configuration ? figure 1 pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ps1 /rsto vdda_sr vssa_sr /vdddet xout xin bout vdda_ux vssa_ux aout a5 sr 2 s r1 vdda_sx v ss a _s x tp1 ps2 a4 a 3 a2 a1 a 0 b cl du d d fsc dcl a d 7 o r s d x a d 6 o r s d r a d 5 or sc l k ad4 vssd vddd ad3 ad2 ad1 ad0 /eaw mclk /act vssa_ur vd da_ u r ain b in /rst vss d v ddd al e /wr o r r/w /r d or /ds /cs /int mti sds2 s ds1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sx 1 s x2 tp2 a6 pin_2.vsd q-smint ? ix pef 81912/ pef 81913 pef 81912/81913 overview data sheet 7 2001-03-30 1.7 block diagram ? figure 2 block diagram clock generation s-transceiver u-tansceiver por/uvd factory tests iom-2 interface p interface (e.g. multiplexed mode) xin xout rst rsto aout bout ain bin tp2 sx2 sx1 sr2 sr1 tp1 led hdlc controller ps1 ps2 mti act eaw mclk int cs wr rd ale ad0-ad7 sds2 sds1 dd du bcl dcl fsc block diagram.vsd vdddet d-channel arbitration fifo m o n c/i tic c d a w d t to p if to p if pef 81912/81913 overview data sheet 8 2001-03-30 1.8 pin definitions and functions ? table 3 pin definitions and functions pin symbol type function 2 vdda_ur C supply voltage for u-receiver (3.3 v 5%) 1 vssa_ur C analog ground (0 v) u-receiver 62 vdda_ux C supply voltage for u-transmitter (3.3 v 5%) 63 vssa_ux C analog ground (0 v) u-transmitter 51 vdda_sr C supply voltage for s-receiver (3.3 v 5%) 52 vssa_sr C analog ground (0 v) s-receiver 46 vdda_sx C supply voltage for s-transmitter (3.3 v 5%) 45 vssa_sx C analog ground (0 v) s-transmitter 29 vddd C supply voltage digital circuits (3.3 v 5%) 30 vssd C ground (0 v) digital circuits 13 vddd C supply voltage digital circuits (3.3 v 5%) 14 vssd C ground (0 v) digital circuits 32 fsc o frame sync: 8-khz frame synchronization signal 31 dcl o data clock: iom ? -2 interface clock signal (double clock): 1.536 mhz 35 bcl o bit clock: the bit clock is identical to the iom ? -2 data rate (768 khz) 33 dd i/o od data downstream: data on the iom ? -2 interface 34 du i/o od data upstream: data on the iom ? -2 interface pef 81912/81913 overview data sheet 9 2001-03-30 8 sds1 o serial data strobe1: programmable strobe signal for time slot and/ or d-channel indication on iom ? -2 7 sds2 o serial data strobe2: programmable strobe signal for time slot and/ or d-channel indication on iom ? -2 12 cs i chip select: a low level indicates a microcontroller access to the q-smint ? ix 26 26 sclk ad5 i i/o serial clock: clock signal of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad5 if the parallel interface is selected non-multiplexed bus mode: data bus data line d5 if the parallel interface is selected 27 27 sdr ad6 i i/o serial data receive: receive data line of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad6 if the parallel interface is selected non-multiplexed bus mode: data bus data line d6 if the parallel interface is selected table 3 pin definitions and functions (contd) pin symbol type function pef 81912/81913 overview data sheet 10 2001-03-30 28 28 sdx ad7 od,o i/o serial data transmit: transmit data line of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad7 if the parallel interface is selected non-multiplexed bus mode: data bus data line d7 if the parallel interface is selected 21 22 23 24 25 ad0 ad1 ad2 ad3 ad4 i/o i/o i/o i/o i/o multiplexed bus mode: address/data bus transfers addresses from the microcontroller to the q-smint ? ix and data between the microcontroller and the q-smint ? ix. non-multiplexed bus mode: data bus. transfers data between the microcontroller and the q-smint ? ix (data lines d0-d4). 36 37 38 39 40 53 54 a0 a1 a2 a3 a4 a5 a6 i i i i i i i non-multiplexed bus mode: address bus transfers addresses from the microcontroller to the q-smint ? ix. for indirect address mode only a0 is valid. multiplexed bus mode not used in multiplexed bus mode. in this case a0-a6 should directly be connected to vdd. 11 rd ds i i read indicates a read access to the registers (intel bus mode). data strobe the rising edge marks the end of a valid read or write operation (motorola bus mode). table 3 pin definitions and functions (contd) pin symbol type function pef 81912/81913 overview data sheet 11 2001-03-30 10 wr r/w i i write indicates a write access to the registers (intel bus mode). read/write a high identifies a valid host access as a read operation and a low identifies a valid host access as a write operation (motorola bus mode). 9 ale i address latch enable an address on the external address/data bus (multiplexed bus type only) is latched with the falling edge of ale. ale also selects the microcontroller interface type (multiplexed or non multiplexed). 5 rst i reset: low active reset input. schmitt-trigger input with hysteresis of typical 360 mv. tie to 1 if not used. 6 rsto od reset output: low active reset output. 15 int od interrupt request: int becomes active if the q-smint ? ix requests an interrupt. 18 mclk o microcontroller clock: clock output for the microcontroller 19 tie to 1 20 eaw i external awake : a low level on eaw during power down activates the clock generation of the q- smint ? ix, i.e. the iom ? -2 interface provides fsc, dcl and bcl for read and write access. 1) 43 sx1 o s-bus transmitter output ( positive ) 44 sx2 o s-bus transmitter output ( negative ) 47 sr1 i s-bus receiver input table 3 pin definitions and functions (contd) pin symbol type function pef 81912/81913 overview data sheet 12 2001-03-30 48 sr2 i s-bus receiver input 60 xin i crystal 1: connected to a 15.36 mhz crystal 59 xout o crystal 2: connected to a 15.36 mhz crystal 64 aout o differential u-interface output 61 bout o differential u-interface output 3 ain i differential u-interface input 4 bin i differential u-interface input 49 vdddet i vdd detection: this pin selects if the v dd detection is active (0) and reset pulses are generated on pin rsto or whether it is deactivated (1) and an external reset has to be applied on pin rst. 16 mti i metallic termination input. input to evaluate metallic termination pulses. tie to 1 if not used. 55 ps1 i power status (primary). the pin status is passed to the overhead bit ps1 in the u frame to indicate the status of the primary power supply (1 = ok). 41 ps2 i power status (secondary). the pin status is passed to the overhead bit ps2 in the u frame to indicate the status of the secondary power supply (1 = ok). 17 act o activation led . indicates the activation status of u- and s- transceiver. can directly drive a led (4 ma). 42 tp1 i test pin 1. used for factory device test. tie to v ss table 3 pin definitions and functions (contd) pin symbol type function pef 81912/81913 overview data sheet 13 2001-03-30 i: input o: output (push-pull) od: output (open drain) 1.8.1 specific pins led pin act a led can be connected to pin act to display four different states (off, slow flashing, fast flashing, on). it displays the activation status of the u- and s-transceiver according to table 4 . or it is programmable via two bits (led1 and led2 in register mode2). with: u_deactivated : deactivated state as defined in chapter 2.4.10.5 . if the simplified state machine is selected: deactivated state and iom ? -2 awaked. u_activated : synchronized 1, synchronized 2, wait for act, transparent, error s/ t, pend. deact. s/t, pend. deact. u as defined in chapter 2.4.10.5 . s-activated : activated state as defined in chapter 2.5.5 . note: optionally, pin act can drive a second led with inverse polarity (connect this additional led to 3.3 v only). 50 tp2 i test pin 2. used for factory device test. tie to v ss 56, 57, 58 res reserved 1) this function of pin eaw is different to that defined in ref. [14] table 4 act states pin act led u_deactivated u_activated s_activated v dd off 1 x x 8hz 8hz 0 0 x 1hz 1hz 0 1 0 gnd on 0 1 1 table 3 pin definitions and functions (contd) pin symbol type function pef 81912/81913 overview data sheet 14 2001-03-30 test modes the test patterns on the s-interface (2 khz single pulses, 96 khz continuous pulses) and on the u-interface (data through, send single pulses) are invoked via c/i codes (tm1, tm2, dt, ssp). setting sres.res_u to 1 forces the u-transceiver into test mode quiet mode (qm), i.e. the u-transceiver is hardware reset. 1.9 system integration ? figure 3 application example q-smint ? ix: low cost intelligent nt the u-transceiver, s-transceiver, the iom ? -2 channels and the hdlc-controller can be controlled and monitored via: a) the parallel or serial microprocessor interface - access of on-chip registers via p interface address/data format - activation/deactivation control of u- and s-transceiver via p interface and c/i handler - q-smint ? ix is monitor channel master - tic bus is transparent on iom ? -2-interface and is used for d-channel arbitration between s-transceiver, on-chip and off-chip hdlc controllers. s u mlt q-smintix pef 81912 pef 81913 u-interface s/t - interface idcc peb2023 hdlc / fifo c513 slicofi-2 hv - slic hv - slic iom-2 p pots interface lcntappl.vsd dc/dc-converter pef 81912/81913 overview data sheet 15 2001-03-30 ? figure 4 control via p interface alternatively, the q-smint ? ix can be controlled via b) the iom ? -2 interface - access of on-chip registers via the monitor channel with header/address/data format (device is monitor slave) - activation/deactivation control of u- and s-transceiver via the c/i channels ci0 and ci1 - tic bus is transparent on iom ? -2-interface and is used for d-channel arbitration between s-transceiver, on-chip and off-chip hdlc controllers. s u c - interface iom -2 iom-2 slave e.g. slicofi-2 c mon c/i register mon c/i1 c/i0 iommaster.vsd pef 81912/81913 overview data sheet 16 2001-03-30 ? figure 5 control via iom ? -2 interface s u iom -2 iom-2 master e.g. utah register c/i1 c/i0 mon iomslave.vsd int pef 81912/81913 functional description data sheet 17 2001-03-30 2 functional description 2.1 microcontroller interfaces the q-smint ? ix supports either a serial or a parallel microcontroller interface. for applications where no controller is connected to the q-smint ? ix microcontroller interface, register programming is done via the iom ? -2 monitor channel from a master device. in such applications the q-smint ? ix operates in the iom ? -2 slave mode (refer to the corresponding chapter of the iom ? -2 monitor handler). the interface selections are all done by pinstrapping. the possible interface selections are listed in table 5 . the selection pins are evaluated when the reset input rst is released. for the pin levels stated in the tables the following is defined: high:dynamic pin value which must be high when the pin level is evaluated v dd , v ss :static high or low level (tied to v dd , v ss ) ? note: for a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to v dd . the microcontroller interface also consists of a microcontroller clock generation at pin mclk, an interrupt request at pin int , a reset input pin rst and a reset output pin rsto . the interrupt request pin int (open drain output) becomes active if the q-smint ? ix requests an interrupt. table 5 interface selection for the q-smint ? ix pins serial /parallel interface pins interface type/mode wr (r/w) rd (ds) cs ale v dd motorola high high parallel high v ss siemens/intel non-mux edge siemens/intel mux v ss v ss serial high v ss serial control interface(sci) v ss v ss iom ? -2 monitor channel (slave mode) pef 81912/81913 functional description data sheet 18 2001-03-30 2.1.1 serial control interface (sci) the serial control interface (sci) is compatible to the spi interface of motorola and to the siemens c510 family of microcontrollers. the sci consists of 4 lines: sclk, sdx, sdr and cs . data is transferred via the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning of a serial access to the registers. the q-smint ? ix latches incoming data at the rising edge of sclk and shifts out at the falling edge of sclk. each access must be terminated by a rising edge of cs . data is transferred in groups of 8 bits with the msb first. pad mode of sdx can be selected open drain or push-pull by programming mode2.ppsdx. figure 6 shows the timing of a one byte read/write access via the serial control interface. pef 81912/81913 functional description data sheet 19 2001-03-30 ? figure 6 serial control interface timing cs sclk sdr sdx cs sclk sdr sdx sci_tim.vsd write access header command/address data 77 0 1 2 3 4 5 61 2 3 4 5 65 6 7 02 3 40 1 `0` write read access header command/address data 77 0 1 2 3 4 5 61 2 3 4 5 6 5 6 7 0 2 3 40 1 `1` read pef 81912/81913 functional description data sheet 20 2001-03-30 2.1.1.1 programming sequences the basic structure of a read/write access to the q-smint ? ix registers via the serial control interface is shown in figure 7 . ? figure 7 serial command structure a new programming sequence starts with the transfer of a header byte. the header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the q-smint ? ix. the possible sequences are listed in table 6 and are described after that. ? table 6 header byte code header byte sequence sequence type access to 40 h adr-data-adr-data non-interleaved address range 00 h -7f h 48 h interleaved 43 h adr-data-data-data read-/write-only address range 00 h -7f h 41 h non-interleaved 49 h interleaved sdr write sequence: read sequence: sdr 7076070 write data address (command) read data 0 1 write read 7076070 header byte 2 byte 3 header byte 2 byte 3 sdx address (command) pef 81912/81913 functional description data sheet 21 2001-03-30 header 40 h : non-interleaved a-d-a-d sequences the non-interleaved a-d-a-d sequences give direct read/write access to the address range 00 h -7f h and can have any length. in this mode sdx and sdr can be connected together allowing data transmission on one line. example for a read/write access with header 40 h : header 48 h : interleaved a-d-a-d sequences the interleaved a-d-a-d sequences give direct read/write access to the address range 00 h -7f h and can have any length. this mode allows a time optimized access to the registers by interleaving the data on sdx and sdr. example for a read/write access with header 48 h : header 43 h : read-/write- only a-d-d-d sequence this mode (header 43 h ) can be used for a fast access to the hdlc fifo data. any address (rdadr, wradr) in the range between 00 h -1f h gives access to the current fifo location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. generally, it can be used for any register access to the address range 00 h -7d h . the sequence can have any length and is terminated by the rising edge of cs . example for a write access with header 43 h : example for a read access with header 43 h : sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx sdr header rdadr sdx rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) pef 81912/81913 functional description data sheet 22 2001-03-30 header 41 h : non-interleaved a-d-d-d sequence this sequence (header 41 h ) allows in front of the a-d-d-d write access a non- interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. generally, it can be used for any register access to the address range 00 h -7d h . the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . example for a read/write access with header 41 h : header 49 h : interleaved a-d-d-d sequence this sequence (header 49 h ) allows in front of the a-d-d-d write access an interleaved a-d-a-d read access. this mode is useful for reading status information before writing to the hdlc xfifo. generally, it can be used for any register access to the address range 00 h -7d h . the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . example for a read/write access with header 49 h : 2.1.2 parallel microcontroller interface the 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. the parallel interface of the q-smint ? ix provides three types of m p busses which are selected via pin ale. the bus operation modes with corresponding control pins are listed in table 7 . ? sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata table 7 bus operation modes bus mode pin ale control pins (1) motorola v dd cs , r/w , ds (2) siemens/intel non-multiplexed v ss cs , wr , rd (3) siemens/intel multiplexed edge cs , wr , rd , ale pef 81912/81913 functional description data sheet 23 2001-03-30 the occurrence of an edge on ale, either positive or negative, at any time during the operation immediately selects the interface type (3). a return to one of the other interface types is possible only if a hardware reset is issued. note: for a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to v dd . a read/write access to the q-smint ? ix registers can be done in multiplexed or non- multiplexed mode. in non-multiplexed mode the register address must be applied to the address bus (a0- a6) for the data access via the data bus (d0-d7). in multiplexed mode the address on the address bus (ad0-ad7) is latched in by ale before a read/write access via the address/data bus is performed. the q-smint ? ix provides two different ways to address the register contents which can be selected with the amod bit in the mode2 register. the address mode after reset is the indirect address mode (amod = 0). reprogramming into the direct address mode (amod = 1) has to take place in the indirect address mode. figure 8 illustrates both register addressing modes. direct address mode (amod = 1): the register address to be read or written is directly set in the way described above. indirect address mode (amod = 0): ? non-muxed: only the lsb of the address bus (a0) ? muxed: only the lsb of the address-data bus (ad0) gets evaluated to address a virtual address (0 h ) and a virtual data (1 h ) register. every access to a target register consists of: ? a write access (muxed or non-muxed) to address to store the target registers address, as well as ? a read access (muxed or non-muxed) from data to read from the target register or ? a write access (muxed or non-muxed) to data to write to the target register pef 81912/81913 functional description data sheet 24 2001-03-30 ? figure 8 direct/indirect register address mode 2.1.3 microcontroller clock generation the microcontroller clock is derived from the unregulated 15.36 mhz clock from the oscillator and provided by the pin mclk. five clock rates are selectable by a programmable prescaler which is controlled by the bits mode1.mclk and mode1.cds corresponding to the following table. table 8 mclk frequencies the clock rate is changed after cs becomes inactive. mode1. mclk bits mclk frequency with mode1.cds = 0 mclk frequency with mode1.cds = 1 0 0 3.84 mhz 7.68 mhz 0 1 0.96 mhz 1.92 mhz 1 0 7.68 mhz 15.36 mhz 1 1 disabled disabled data a0 address 1h 0h data data a6 - a0 00h 01h 02h 03h 04h 7ch 7dh 7eh 7fh d7 - d0 d7 - d0 indirect address mode amod = 0 (default) direct address mode amod = 1 regacces.vsd pef 81912/81913 functional description data sheet 25 2001-03-30 2.2 reset generation figure 9 shows the organization of the reset generation of the q-smint ? ix. ?. figure 9 reset generation of the q-smint ? ix 1) reset source selection the internal reset sources c/i code change and watchdog timer can be output at the low active reset pin rsto . these reset sources can be selected with the rss2,1 bits in the mode1 register according to table 9 . 1) the or-gates shall illustrate in a symbolic way, that source a active or source b active is forwarded. the real polarity of the different sources is not considered. watchdog c/i0 code change (exchange awake) software reset register (sres) reset functional block res_ci res_s res_hdlc res_u internal reset of all registers 3 1 3 1 por/uvd vdddet rst pin rss2,1 rss2,1 rss1 resetgen.vsd rsto 0,1= open 0 1 1,x 0,0 125s t 250s t = 125s deacti- vation delay vdddet 0 1 reset mode1 register 0 1 pef 81912/81913 functional description data sheet 26 2001-03-30 the internal reset sources set the mode1 register to its reset value. table 9 reset source selection ? ? c/i code change (exchange awake) a change in the downstream c/i channel (c/i0) generates a reset pulse of 125 s t 250 s. ? watchdog timer after the selection of the watchdog timer (rss = 11) an internal timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1- and wtc2 bits in the following sequence to reset and restart the watchdog timer: otherwise the timer expires and a wov-interrupt (ista register) together with a reset out pulse on pin rsto of 125 s is generated. deactivation of the watchdog timer is only possible with a hardware reset (including expiration of the watchdog timer). as in the scout-s, the watchdog timer is clocked with the iom ? -2 clocks and works only if the internal iom ? -2 clocks are active. hence, the power consumption is minimized in state power down. software reset register (sres) several main functional blocks of the q-smint ? ix can be reset separately by software setting the corresponding bit in the sres register. this is equivalent to a hardware reset of the corresponding functional block. the reset state is activated as long as the bit is set to 1. rss2 bit 1 rss1 bit 0 c/i code change watchdog timer por/uvd 1) and rst 1) por/uvd can be enabled/disabled via pin vdddet 0 0 -- -- x 0 1 /rsto disabled (= high impedance) 10x--x 11 -- x x wtc1 wtc2 1. 2. 1 0 0 1 pef 81912/81913 functional description data sheet 27 2001-03-30 external reset input at the rst input an external reset can be applied forcing the q-smint ? ix in the reset state. this external reset signal is additionally fed to the rsto output. after release of an external reset, the m c has to wait for min. t m c before it starts read or write access to the q-smint ? ix (see table 45 ). reset ouput if vdddet is active, then the deactivation of a reset output on rsto is delayed by t deact (see table 46 ). reset generation the q-smint ? ix has an on-chip reset generator based on a power-on reset (por) and under voltage detection (uvd) circuit (see table 46 ). the por/uvd requires no external components. the por/uvd circuit can be disabled via pin vdddet . the requirements on v dd ramp-up during power-on reset are described in chapter 5.6.5 . clocks and data lines during reset during reset the data clock (dcl), the bit clock (bcl), the microcontroller clock 1) (mclk) and the frame synchronization (fsc) keep running. during reset dd and du are high; with the exception of: ? the output c/i code from the u-transceiver on dd iom ? -2 channel 0 is dr = 0000 (value after reset of register ucir = 00 h ) ? the output c/i code from the s-transceiver on du iom ? -2 channel 1 is tim = 0000. 1) during a power-on/uvd reset, the microcontroller clock mclk is not running, but starts running as soon as timer t deac is started. pef 81912/81913 functional description data sheet 28 2001-03-30 2.3 iom -2 interface the q-smint ? ix supports the iom ? -2 interface in terminal mode (dcl=1.536 mhz) according to the iom ? -2 reference guide [13]. 2.3.1 iom ? -2 functional description the iom ? -2 interface consists of four lines: fsc, dcl, dd, du and optionally bcl. the rising edge of fsc indicates the start of an iom ? -2 frame. the dcl and the bcl clock signals synchronize the data transfer on both data lines du and dd. the dcl is twice the bit rate, the bcl rate is equal to the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle and sampled at the falling edge of the second clock cycle. with bcl the bits are shifted out with the rising edge and sampled with the falling edge of the single clock cycle. the iom ? -2 interface can be enabled/disabled with the dis_iom bit in the iom_cr register. the fsc signal is an 8 khz frame sync signal. the number of pcm timeslots on the receive and transmit lines is determined by the frequency of the dcl clock (or bcl), with the 1.536 mhz (bcl=768 khz) clock 3 channels consisting of 4 timeslots each are available. iom ? -2 frame structure of the q-smint ? ix the frame structure on the iom ? -2 data ports (du,dd) of the q-smint ? ix with a dcl clock of 1.536 mhz (or bcl=768 khz) and if tic bus is not disabled (iom_cr.tic_dis) is shown in figure 10 . ? figure 10 iom -2 frame structure of the q-smint ? ix macro_19 pef 81912/81913 functional description data sheet 29 2001-03-30 the frame is composed of three channels ? channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (mon0) and a command/indication channel (ci0) for control and programming of e.g. the u-transceiver. ? channel 1 contains two 64-kbit/s intercommunication channels (ic), a monitor programming channel (mon1) and a command/indication channel (ci1) for control and programming of e.g. the s-transceiver. ? channel 2 is used for d-channel access mechanism (tlc-bus, s/g bit). additionally, channel 2 supports further ic and mon channels. 2.3.2 iom ? -2 handler the iom ? -2 handler offers a great flexibility for handling the data transfer between the different functional units of the q-smint ? ix and voice/data devices connected to the iom ? -2 interface. additionally it provides a microcontroller access to all time slots of the iom ? -2 interface via the four controller data access registers (cda). the pcm data of the functional units ? s-transceiver (s) and the ? controller data access (cda) can be configured by programming the time slot and data port selection registers (tsdp). with the tss bits (time slot selection) the pcm data of the functional units can be assigned to each of the 12 pcm time slots of the iom ? -2 frame. with the dps bit (data port selection) the output of each functional unit is assigned to du or dd respectively. the input is assigned vice versa. with the control registers (cr) the access to the data of the functional units can be controlled by setting the corresponding control bits (en, swap). the iom ? -2 handler also provides access to the ? u and s transceiver ? monitor channel ? c/i channels (ci0,ci1) ? tic bus (tic) and ? d- and/or b-channel for hdlc control the access to these channels is controlled by the registers s_cr, hci_cr and mon_cr. the iom ? -2 interface with the two serial data strobes (sds1,2) is controlled by the control registers iom_cr, sds1_cr and sds2_cr. the following figure 11 shows the architecture of the iom ? -2 handler. pef 81912/81913 functional description data sheet 30 2001-03-30 ? figure 11 architecture of the iom ? -2 handler 21150_0 7 control data access (tsdp, dps, en, swap, tbm, mcda, sti) cda registers cda10 cda11 cda20 cda21 cda_tsdpxy cda_crx mcda sti msti asti controller data access (cda) control monitor data mon_cr tic bus disable iom_cr control hdlc b1-data en b2-data en d-data en hci_cr control c/i1 data control transceiver data access (tss, dps, en) s_tsdp_b1 s_tsdp_b2 s_cr ddata d/b1/b2 data c/i0 data c/i1 data c/i0 data tic bus data monitor data cda data transceiver data (tr=u/s) tr_b1_x tr_b2_x tr_d_x tr_b1_r tr_b2_r tr_d_r mon handler tic c/i0 c/i1 data b1/b2/d-ch fifos microcontroller interface sds1/2_cr iom_cr (en, tlen, tss) iom-2 interface (en, od) du dd fsc dcl bcl/sclk sds1 sds2 iom-2 handler tr represents the u and s transceiver pef 81912/81913 functional description data sheet 31 2001-03-30 2.3.2.1 controller data access (cda) the four controller data access registers (cda10, cda11, cda20, cda21) provide microcontroller access to the 12 iom ? -2 time slots and more: ? looping of up to four independent pcm channels from du to dd or vice versa over the four cda registers ? shifting or switching of two independent pcm channels to another two independent pcm channels on both data ports (du, dd). between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. if this is not the case a switching function is performed. ? monitoring of up to four time slots on the iom ? -2 interface simultaneously ? microcontroller read and write access to each pcm channel the access principle, which is identical for the two channel register pairs cda10/11 and cda20/21, is illustrated in figure 12 . the index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. the prefix cda_ from the register names has been omitted for simplification. to each of the four cdaxy data registers a tsdpxy register is assigned by which the time slot and the data port can be determined. with the tss (time slot selection) bits a time slot from 0...11 can be selected. with the dps (data port selection) bit the output of the cdaxy register can be assigned to du or dd respectively. the time slot and data port for the output of cdaxy is always defined by its own tsdpxy register. the input of cdaxy depends on the swap bit in the control registers crx. if the swap bit = 0 (swap is disabled) the time slot and data port for the input and output of the cdaxy register is defined by its own tsdpxy register. if the swap bit = 1 (swap is enabled) the input port and time slot of the cdax0 is defined by the tsdp register of cdax1 and the input port and time slot of cdax1 is defined by the tsdp register of cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 swapped to cdax0. the output timeslots are not affected by swap. the input and output of every cdaxy register can be enabled or disabled by setting the corresponding en (-able) bit in the control register cdax_cr. if the input of a register is disabled the output value in the register is retained. usually one input and one output of a functional unit (transceiver, hdlc controller, cda register) is programmed to a timeslot on iom ? -2 (e.g. for b-channel transmission in upstream direction the s-transceiver writes data onto iom ? -2 and the u-transceiver reads data from iom ? -2). for monitoring data in such cases a cda register is programmed as described below under monitoring data. besides that none of the iom ? -2 timeslots must be assigned more than one input and output of any functional unit. pef 81912/81913 functional description data sheet 32 2001-03-30 ?. figure 12 data access via cdax0 and cdax1 register pairs looping and shifting data figure 13 gives examples for typical configurations with the above explained control and configuration possibilities with the bits tss, dps, en and swap in the registers tsdpxy or cdax_cr: a) looping iom ? -2 time slot data from du to dd or vice versa (swap = 0) b) shifting data from tsa to tsb and tsc to tsd in both transmission directions (swap = 1) c) switching data from tsa to tsb and looping from du to dd or switching tsc to tsd and looping from dd to du . tsa is programmed in tsdp10, tsb in tsdp11, tsc in tsdp20 and tsd in tsdp21. x = 1 or 2; a,b = 0...11 iom_hand.fm4 du cdax1 control register cda_crx dd 1 1 time slot selection (tss) 1 data port cda_tsdpx1 0 1 0 1 1 0 1 1 enable input (en_o0) output cda_tsdpx0 1 0 cdax0 1 (en_i0) (en_i1) input enable output (en_o1) selection (dps) data port selection (dps) selection (tss) time slot tsa tsa tsb tsb input swap (swap) pef 81912/81913 functional description data sheet 33 2001-03-30 ? figure 13 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) switching and looping data tsa tsb tsc tsd cda10 cda11 cda20 cda21 tsa tsb tsc tsd du dd tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd b) shifting data a) looping data .tss: .dps .swap 0 1 1 0 0 0 tsa tsb tsc tsd .tss: .dps .swap 1 1 0 1 0 1 tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd c) switching data tsa tsb tsc tsd .tss: .dps .swap 1 1 1 0 0 1 pef 81912/81913 functional description data sheet 34 2001-03-30 figure 14 shows the timing of looping tsa from du to dd via cdaxy register. tsa is read in the cdaxy register from du and is written one frame later on dd. figure 15 shows the timing of shifting data from tsa to tsb on du(dd). in figure 15 a) shifting is done in one frame because tsa and tsb didnt succeed directly one another (a = 0...9 and b 3 a+2) . in figure 15 b) shifting is done from one frame to the following frame. this is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). at looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). sti and stov are explained in the section synchronous transfer. if there is no controller intervention the looping and shifting is done autonomously. ?. figure 14 data access when looping tsa from du to dd tsa du tsa fsc cdaxy c rd wr ack stov tsa dd tsa sti *) if access by the c is required *) pef 81912/81913 functional description data sheet 35 2001-03-30 ? figure 15 data access when shifting tsa to tsb on du (dd) tsa du tsb fsc cdaxy c rd wr ack stov sti tsa sti tsa fsc cdaxy c rd wr ack stov sti tsb tsa tsb (dd) (a,b: 0...11 and (b = a+1 or b pef 81912/81913 functional description data sheet 37 2001-03-30 monitoring tic bus monitoring the tic bus (ts11) is handled as a special case. the tic bus can be monitored with the registers cdax0 by setting the en_tbm (enable tic bus monitoring) bit in the control registers crx. the tsdpx0 must be set to 08 h for monitoring from du or 88 h for monitoring from dd. by this it is possible to monitor the tic bus (ts11) and the odd numbered d-channel (ts3) simultaneously on du and dd. synchronous transfer while looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the synchronous transfer overflow interrupt (stov). the microcontroller access to each of the cdaxy registers can be synchronized by means of four programmable synchronous transfer interrupts (stixy) 1) and synchronous transfer overflow interrupts (stovxy) 2) in the sti register. depending on the dps bit in the corresponding tsdpxy register the stixy is generated two (for dps=0) or one (for dps=1) bcl clock after the selected time slot (cda_tsdpxy.tss). one bcl clock is equivalent to two dcl clocks. in the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (sti/stov) out of the four cda interrupt pairs (sti10/stov10, sti11/ stov11, sti20/stov20, sti21/stov21). a stovxy 0 is related to its stixy 0 and is only generated if stixy 0 is enabled and not acknowledged. however, if stixy 0 is masked, the stovxy0 is generated for any other stixy1 which is enabled and not acknowledged. table 10 gives some examples for that. it is assumed that a stov interrupt is only generated because a sti interrupt was not acknowledged before. in example 1 only the stixy 0 is enabled and thus stixy 0 is only generated. if no sti is enabled, no interrupt will be generated even if stov is enabled (example 2). in example 3 stixy 0 is enabled and generated and the corresponding stovxy 0 is disabled. stixy 1 is disabled but its stovxy 1 is enabled, and therefore stovxy 1 is generated due to stixy 0 . in example 4 additionally the corresponding stovxy 0 is enabled, so stovxy 0 and stovxy 1 are both generated due to stixy 0 . in example 5 additionally the stixy 1 is enabled with the result that stovxy 0 is only generated due to stixy 0 and stovxy 1 is only generated due to stixy 1 . compared to the previous example stovxy 0 is disabled in example 6, so stovxy 0 is not generated and stovxy 1 is only generated for stixy 1 but not for stixy 0 . 1) in order to enable the sti interrupts the input of the corresponding cda register has to be enabled. this is also valid if only a synchronous write access is wanted. the enabling of the output alone does not effect an sti interrupt. 2) in order to enable the stov interrupts the output of the corresponding cda register has to be enabled. this is also valid if only a synchronous read access is wanted. the enabling of the input alone does not effect an interrupt. pef 81912/81913 functional description data sheet 38 2001-03-30 ? compared to example 5 in example 7 a third stovxy 2 is enabled and thus stovxy2 is generated additionally for both stixy 0 and stixy 1 . a stov interrupt is not generated if all stimulating sti interrupts are acknowledged. a stixy must be acknowledged by setting the ackxy bit in the asti register two bcl clock (for dps=0) or one bcl clocks (for dps=1) before the time slot which is selected for the appropriate stixy. the interrupt structure of the synchronous transfer is shown in figure 17 . table 10 examples for synchronous transfer interrupts enabled interrupts (register msti) generated interrupts (register sti) stistovstistov xy 0 -xy 0 - example 1 -xy 0 - - example 2 xy 0 xy 1 xy 0 xy 1 example 3 xy 0 xy 0 ; xy 1 xy 0 xy 0 ; xy 1 example 4 xy 0 ; xy 1 xy 0 ; xy 1 xy 0 xy 1 xy 0 xy 1 example 5 xy 0 ; xy 1 xy 1 xy 0 xy 1 - xy 1 example 6 xy 0 ; xy 1 xy 0 ; xy 1 ; xy 2 xy 0 xy 1 xy 0 ; xy 2 xy 1 ; xy 2 example 7 pef 81912/81913 functional description data sheet 39 2001-03-30 ?. figure 17 interrupt structure of the synchronous data transfer figure 18 shows some examples based on the timeslot structure. figure a) shows at which point in time a sti and stov interrupt is generated for a specific timeslot. figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. cic st mos s wov cic st mos s wov int sti11 ista mask msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 ack11 asti ack10 ack20 ack21 u u hdlc hdlc tin tin pef 81912/81913 functional description data sheet 40 2001-03-30 ?. figure 18 examples for the synchronous transfer interrupt control with one stixy enabled ? . xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 a) interrupts for data access to time slot 0 (b1 after reset), msti.sti10 and msti.stov10 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '1' '1' '1' '0' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 b) interrupts for data access to time slot 0 (b1 after reset), stov interrupt used as flag for "last possible cda access"; msti.sti10 and msti.stov20 enabled c) interrupts for data access to time slot 0 and 1 (b1 and b2 after reset), msti.sti10, msti.stov10, msti.sti11 and msti.stov11 enabled sti_stov.vsd xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '0' '1' '1' msti.stovxy: '0' '0' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 d) interrupts for data access to time slot 0 (b1 after reset), stov20 interrupt used as flag for "last possible cda access", stov10 interrupt used as flag for "cda access failed"; msti.sti10, msti.stov10 and msti.stov20 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '0' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 : stov interrupt generated for a not acknowledged sti interrupt : sti interrupt generated pef 81912/81913 functional description data sheet 41 2001-03-30 2.3.2.2 serial data strobe signal for time slot oriented standard devices at the iom ? -2 interface, the q-smint ? ix provides two independent data strobe signals sds1 and sds2. the two strobe signals can be generated with every 8-khz-frame and are controlled by the registers sds1/2_cr. by programming the tss bits and three enable bits (ens_tss, ens_tss+1, ens_tss+3) a data strobe can be generated for the iom ? -2 time slots ts, ts+1 and ts+3 (bit7,6) and the combinations of them. the data strobes for ts and ts+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for ts+3 is always 2 bits long (bit7, bit6). ? figure 19 data strobe signal generation fsc dd,du m r m x d ci0 sds1,2 (example1) sds1,2 (example2) sds1,2 (example3) tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' ='0' ='1' ='0' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' ='1' ='1' ='0' tss ens_tss ens_tss+1 ens_tss+3 example 3: = '0 h ' ='1' ='1' ='1' ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 strobe.vsd pef 81912/81913 functional description data sheet 42 2001-03-30 figure 19 shows three examples for the generation of a strobe signal. in example 1 the sds is active during channel b2 on iom ? -2, whereas in the second example during ic2 and mon1. the third example shows a strobe signal for 2b+d channels which is used e.g. at an idsl (144 kbit/s) transmission. 2.3.3 iom ? -2 monitor channel the iom ? -2 monitor channel is utilized for information exchange between the q- smint ? ix and other devices in the monitor channel. the montior channel data can be controlled by the bits in the monitor control register (mon_cr). for the transmission of the monitor data one of the 3 iom ? -2 channels can be selected by setting the monitor channel selection bits (mcs) in the monitor control register (mon_cr). the dps bit in the same register selects between an output on du or dd respectively and with en_mon the monitor data can be enabled/disabled. the default value is monitor channel 0 (mon0) enabled and transmission on dd. the monitor channel of the q-smint ? ix can be used in the following applications (refer also to figure 4 and figure 5 ): ? as a master device the q-smint ? ix can program and control other devices (e.g. psb 2161) attached to the iom ? -2, which therefore, do not need a microcontroller interface. ? as a slave device the q-smint ? ix is programmed and controlled from a master device on iom ? -2 (e.g. utah). this is used in applications where no microcontroller is connected directly to the q-smint ? ix. the monitor channel operates according to the iom ? -2 reference guide [13]. note: in contrast to the intc-q, the q-smint ? ix does neither issue nor react on monitor commands (mon0,1,2,8). instead, the q-smint ? ix operated in iom ? -2 slave mode must be programmed via new monitor channel concept (see chapter 2.3.3.4 ), which provides full register access. the monitor time out procedure is available. reporting of the q-smint ? ix is performed via interrupts. 2.3.3.1 handshake procedure the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted once per 8-khz frame until the transfer is acknowledged via the mr bit. pef 81912/81913 functional description data sheet 43 2001-03-30 the monitor channel protocol is described in the following section and figure 22 shall illustrate this. the relevant control and status bits for transmission and reception are listed in table 11 and table 12 . table 11 transmit direction control/ status bit register bit function control mocr mxc mx bit control mie transmit interrupt (mda, mab, mer) enable status mosr mda data acknowledged mab data abort msta mac transmission active table 12 receive direction control/ status bit register bit function control mocr mrc mr bit control mre receive interrupt (mdr) enable status mosr mdr data received mer end of reception pef 81912/81913 functional description data sheet 44 2001-03-30 ? figure 20 monitor channel protocol (iom ? -2) before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a 0 in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to 1. this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates a mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to 1 to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. itd10032 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mie = 1 mox = adr mxc = 1 mac = 1 mox = data1 mda int. mda int. mda int. mxc = 0 mdr int. rd mor (=adr) mrc = 1 mdr int. mdr int. mrc = 0 mer int. p p 125 s rd mor (=data1) rd mor (=data2) mox = data2 mac = 0 pef 81912/81913 functional description data sheet 45 2001-03-30 in addition, it enables other monitor channel interrupts by setting monitor interrupt enable (mie) to 1. as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to 0. this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate a mda interrupt status. this "mda interrupt C write data C mdr interrupt C read data C mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to 0. this enforces an inactive (1) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to 0. during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to 0. an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter. the monitor transfer protocol rules are summarized in the following section ? a pair of mx and mr in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission . ?a start of a transmission is initiated by the transmitter by setting the mxc bit to 1 enabling the internal mx control. the receiver acknowledges the received first byte by setting the mr control bit to 1 enabling the internal mr control. ? the internal mx, mr control indicates or acknowledges a new byte in the mon slot by toggling mx, mr from the active to the inactive state for one frame. ? two frames with the mr-bit set to inactive indicate a receiver request for abort . ? the transmitter can delay a transmission sequence by sending the same byte continuously. in that case the mx-bit remains active in the iom ? -2 frame following the first byte occurrence. delaying a transmission sequence is only possible while the receiver mr-bit and the transmitter mx-bit are active. pef 81912/81913 functional description data sheet 46 2001-03-30 ? since a double last-look criterion is implemented the receiver is able to receive the mon slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. ? to control this handshake procedure a collision detection mechanism is implemented in the transmitter. this is done by making a collision check per bit on the transmitted monitor data and the mx bit. ? monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. ? two frames with the mx bit in the inactive state indicates the end of a message (eom). ? transmission and reception of monitor messages can be performed simultaneously. this feature is used by the device to send back the response before the transmission from the controller is completed (the device does not wait for eom from controller). 2.3.3.2 error treatment in case the device does not detect identical monitor messages in two successive frames, transmission is not aborted. instead the device will wait until two identical bytes are received in succession. a transmission is aborted by the device if ? an error in the mr handshaking occurs ? a collision on the iom ? -2 bus of the monitor data or mx bit occurs ? the transmission time-out timer expires a reception is aborted by the device if ? an error in the mx handshaking occurs or ? an abort request from the opposite device occurs mx/mr treatment in error case in the master mode the mx/mr bits are under control of the microcontroller through mxc or mrc, respectively. an abort is indicated by an mab interrupt or mer interrupt, respectively. in the slave mode the mx/mr bits are under control of the device. an abort is always indicated by setting the mx/mr bit inactive for two or more iom ? -2 frames. the controller must react with eom. figure 21 shows an example for an abort requested by the receiver, figure 22 shows an example for an abort requested by the transmitter and figure 23 shows an example for a successful transmission. pef 81912/81913 functional description data sheet 47 2001-03-30 ? figure 21 monitor channel, transmission abort requested by the receiver ? figure 22 monitor channel, transmission abort requested by the transmitter ? figure 23 monitor channel, normal end of transmission mx (du) iom -2 frame no. 1 2 345 67 eom mr (dd) 1 0 1 0 mon_rec-abort.vsd abort request from receiver mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_tx-abort.vsd abort request from transmitter mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_norm.vsd 8 pef 81912/81913 functional description data sheet 48 2001-03-30 2.3.3.3 monitor channel programming as a master device the master mode is selected by default if one of the microcontroller interfaces is selected. the monitor data is written by the microcontroller in the mox register and transmitted via iom ? -2 dd(du) line to the programmed/controlled device e.g. arcofi- ba psb 2161. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr. 2.3.3.4 monitor channel programming as a slave device monitor slave mode can be selected by pinstrapping the microcontroller interface pins according to table 5 . all programming data required by the device is received in the monitor time slot on the iom ? -2 and is transferred to the mor register. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter 2.3.3.1 . the first byte of the monitor message must contain in the higher nibble the monitor channel address code which is 1000 for the q-smint ? ix. the lower nibble distinguishes between a programming command and an identification command. identification command in order to be able to identify unambiguously different hardware designs of the q- smint ? ix by software, the following identification command is used: the q-smint ? ix responds to this identification sequence by sending a identification sequence: design: six bit code, specific for each device in order to identify differences in operation (see id - identification register on page 198 ). this identification sequence is usually done once, when the q-smint ? ix is connected for the first time. this function is used so that the software can distinguish between different possible hardware configurations. however this sequence is not compulsory. programming sequence the programming sequence is characterized by a 1 being sent in the lower nibble of the received address code. the data structure after this first byte is equivalent to the structure of the serial control interface described in chapter chapter 2.1.1 . du 1st byte value 1 0 0 0 0 0 0 0 du 2nd byte value 0 0 0 0 0 0 0 0 dd 1st byte value 1 0 0 0 0 0 0 0 dd 2nd byte value 0 0 design pef 81912/81913 functional description data sheet 49 2001-03-30 ? all registers can be read back when setting the r/w bit to 1. the q-smint ? ix responds by sending his iom ? -2 specific address byte (81 h ) followed by the requested data. note: application hint: it is not allowed to disable the mx- and mr-control in the programming device at the same time! first, the mx-control must be disabled, then the c has to wait for an end of reception before the mr-control may be disabled. otherwise, the q- smint ? ix does not recognize an end of reception. 2.3.3.5 monitor time-out procedure to prevent lock-up situations in a monitor transmission a time-out procedure can be enabled by setting the time-out bit (tout) in the monitor configuration register (mconf). an internal timer is always started when the transmitter must wait for the reply of the addressed device or for transmit data from the microcontroller. after 40 iom ? -2 frames (5 ms) without reply the timer expires and the transmission will be aborted with an eom (end of message) command by setting the mx bit to 1 for two consecutive iom ? -2 frames. 2.3.3.6 monitor interrupt logic figure 24 shows the interrupt structure of the monitor handler. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable (mre) and mr bit control (mrc). the monitor channel end of reception mer, monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie. mre set to 0 prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is set to 1 but mrc is set to 0, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are set to 1, mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. additionally, a mrc set to 1 enables the control of the mr handshake bit according to the monitor channel protocol. du 1st byte value 1 0 0 0 0 0 0 1 du 2nd byte value header byte du 3rd byte value r/w command/ register address du 4th byte value data 1 du (nth + 3) byte value data n pef 81912/81913 functional description data sheet 50 2001-03-30 ? figure 24 monitor interrupt structure 2.3.4 c/i channel handling the command/indication channel carries real-time status information between the q- smint ? ix and another device connected to the iom ? -2. 1) c/i0 channel lies in iom ? -2 channel 0 and access may be arbitrated via the tic bus access protocol. in this case the arbitration is done in iom ? -2 channel 2. the c/i0 channel is accessed via register cir0 (received c/i0 data from dd) and register cix0 (transmitted c/i0 data to du). the c/i0 code is four bits long. in the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated any time a change occurs (ista.cic). c/i0 only: a new code must be found in two consecutive iom ? -2 frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix0 is continuously transmitted in c/i0. 2) a second c/i channel (called c/i1) lies in iom ? -2 channel 1 and is used to convey real time status information of the on-chip s-transceiver or an external device. the c/i1 channel consists of four or six bits in each direction. the width can be changed from 4 bit to 6 bit by setting bit cix1.cicw. in 4-bit mode 6-bits are written whereby the higher 2 bits must be set to 1 and 6-bits are read whereby only the 4 lsbs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). cic st mos s wov int ista cic st mos s wov u u mask mre mdr mie mda mer mab mosr mocr tin tin hdlc hdlc pef 81912/81913 functional description data sheet 51 2001-03-30 the c/i1 channel is accessed via registers cir1 and cix1. the connection of cir1 and cix1 to dd and du, respectively, can be selected by setting bit hci_cr.dps_ci1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. cic interrupt logic figure 25 shows the cic interrupt structure. the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e in the cix1 register. in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. the cir0 is buffered with a fifo size of two. if a second code change occurs in the received c/i channel 0 before the first one has been read, immediately after reading of cir0 a new interrupt will be generated and the new code will be stored in cir0. if several consecutive codes are detected, only the first and the last code are obtained at the first and second register read, respectively. for cir1 no fifo is available. the actual code of the received c/i channel 1 is always stored in cir1. ? figure 25 cic interrupt structure 2.3.5 d-channel access control the upstream d-channel is arbitrated between the s-bus, the internal hdlc controller and external hdlc controllers via the tic bus (s/g, bac, tba bits) according to the cic st mos s wov int ista mask cic1 ci1e cic0 cir0 cix1 cic st mos s wov u u hdlc hdlc tin tin pef 81912/81913 functional description data sheet 52 2001-03-30 iom ? -2 reference guide 1) . further to the implementation in the intc-q it is possible, to set the priority (8 or 10) of all hdlc-controllers connected to iom ? -2, which is particularly useful for use of the q-smint ? ix together with the utah. 2.3.5.1 application example for d-channel access control figure 26 shows a scenario for the local d-channel arbitration between the s-bus and the microcontroller. ? figure 26 d-channel arbitration: m c has no hdlc and no direct access to tic bus 2.3.5.2 tic bus handling the tic bus is implemented to organize the access to the c/i0-channel and to the d- channel from up to 7 d-channels hdlc controllers. the arbitration mechanism must be activated by setting modeh.dim2-0=00x. the arbitration mechanism is implemented in the last octet in iom ? -2 channel 2 of the iom ? -2 interface (see figure 27 ). an access request to the tic bus may either be generated by software (c access to the c/i0-channel via cix0 register) or by an internal or an external d-channel hdlc controller (transmission of an hdlc frame in the d- channel). a software access request to the bus is effected by setting the bac bit in register cix0 to 1 (resulting in bac = 0 on iom ? -2). 1) the a/b-bit is not supported by the u-transceiver s u hdlc p - i/f iom-2 i/f arbitr. c e.g. c513, c161-ri iom-2 prio e-bit bac, tba s/g d d . cix0 cir0 c writes data into fifo, transmission happens automatically q-smintix delivers an interrupt, when transmission is complete q-smint ? ix pef 81912/81913 functional description data sheet 53 2001-03-30 in the case of an access request by the q-smint ? ix, the bus accessed-bit bac (bit 5 of last octet of ch2 on du, see figure 27 ) is checked for the status "bus free, which is indicated by a logical 1. if the bus is free, the q-smint ? ix transmits its individual tic bus address tad programmed in the cix0 register (cix0.tba2-0). while being transmitted the tic bus address tad is compared bit by bit with the value read back on du. if a sent bit set to 1 is read back as 0 because of the access of an external device with a lower tad, the q-smint ? ix withdraws immediately from the tic bus, i.e. the remaining tad bits are not transmitted. the tic bus is occupied by the device which sends and reads back its address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. this one will set bac=0 on tic bus and starts d-channel transmission in the same frame. ? figure 27 structure of last octet of ch2 on du when the tic bus is seized by the q-smint ? ix, the bus is identified to other devices as occupied via the du ch2 bus accessed-bit state 0 until the access request is withdrawn. after a successful bus access, the q-smint ? ix is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. if none of the devices connected to the iom ? -2 interface request access to the d and c/ i0 channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i0 channels. note: bit bac (cix0 register) should be reset by the m c when access is no more requested, to grant other devices access to the d and c/i0 channels. 2.3.5.3 stop/go bit handling the availability of the du d channel is indicated in bit 5 "stop/go" (s/g) of the last octet in dd channel 2 ( figure 28 ). the arbitration mechanism must be activated by setting modeh.dim2-0=0x1. s/g = 1 : stop s/g = 0 : go b1 b2 mon0 d ci0 ic1 ic2 mon1 ci1 mx mr mx mr bac tad bus accessed ("1" no tic-bus access) itd02575.vsd bac tad 21 0 tic-bus address (tad 2 - 0) du pef 81912/81913 functional description data sheet 54 2001-03-30 the stop/go bit is available to other layer-2 devices connected to the iom ? -2 interface to determine if they can access the d channel in upstream direction. ? figure 28 structure of last octet of ch2 on dd 2.3.5.4 d-channel arbitration in intelligent nt applications (selected via register s_mode.mode2-0) the q- smint ? ix has to share the upstream d-channel with one or more d-channel controllers on the iom ? -2 interface and with all connected tes on the s interface. the s-transceiver incorporates an elaborate state machine for d-channel priority handling on iom ? -2 ( chapter 2.3.5.5 ). for the access to the d-channel a similar arbitration mechanism as on the s interface (writing d-bits, reading back e-bits) is performed for all d-channel sources on iom ? -2. due to this an equal and fair access is guaranteed for all d-channel sources on both the s interface and the iom ? -2 interface. the access to the upstream d-channel is handled via the s/g bit for the hdlc controllers and via e-bit for all connected terminals on s (e-bits are inverted to block the terminals on s). furthermore, if more than one hdlc source is requesting d-channel access on iom ? -2 the tic bus mechanism is used (see chapter 2.3.5.2 ). the arbiter permanently counts the 1s in the upstream d-channel on iom ? -2. if the necessary number of 1s is counted and an hdlc controller on iom ? -2 requests upstream d-channel access (bac bit is set to 0), the arbiter allows this d-channel controller immediate access and blocks other tes on s (e-bits are inverted). similar as on the s-interface the priority for d-channel access on iom ? -2 can be configured to 8 or 10 (s_cmd.dprio). the configuration settings of the q-smint ? ix in intelligent nt applications are summarized in table 13 . b1 b2 mon 0 d ci0 ic1 ic2 mon1 ci1 mx mr mx mr s/g a/b s/g a/b stop/go available/blocked itd09693.vsd dd pef 81912/81913 functional description data sheet 55 2001-03-30 ? note: for mode selection in the s_mode register the mode1/2 bits are used to select intelligent nt mode, mode0 selects nt or lt-s state machine. with the configuration settings shown above the q-smint ? ix in intelligent nt applications provides for equal access to the d-channel for terminals connected to the s-interface and for d-channel sources on iom ? -2. 2.3.5.5 state machine of the d-channel arbiter figure 29 gives a simplified view of the state machine of the d-channel arbiter. cnt is the number of 1 on the iom ? -2 d-channel and bac corresponds to the bac-bit on iom ? -2. the number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). table 13 q-smint ? ix configuration settings in intelligent nt applications functional block configuration description configuration setting layer 1 select intelligent nt mode s-transceiver mode register: s_mode.mode0 = 0 (nt state machine) or s_mode.mode0 = 1 (lt-s state machine) s_mode.mode1 = 1 s_mode.mode2 = 1 layer 2 enable s/g bit and tic bus evaluation d-channel mode register: modeh.dim2-0 = 001 pef 81912/81913 functional description data sheet 56 2001-03-30 ? figure 29 state machine of the d-channel arbiter (simplified view) 1) table 14 lists the major differences of the d-channel arbiters state machine between q- smint ? ix and intc-q [12] ?: 1) if the s-transceiver is reset by sres.res_s = 1 or disabled by s_conf0.dis_tr = 1, then the d-channel arbiter is in state ready (s/g = 1), too. the s/g evaluation of the hdlc has to be disabled in this case; otherwise, the hdlc is not able to send data. table 14 major differences d-channel arbiter intc-q and q-smint ? ix intc-q q-smint ? ix state idle (s/g=0, e=d) automatically entered from state ready or s access after cnt=n not available, initial state is ready (s/g=1, e=d) bac-bit ignored local hdlc must tie bac = 0 to enter state local access d-channel inhibit not possible s-mode.dch_inh alternative to bac-bit to enter state local access bac=1& dci=0 ready s/g = 1 e=d 1)2) rst=0, a/b=0, mode=0xx d-channel_arbitration.vsd bac = d.c. dci = 0 s access s/g = 1 e = d 1) &cnt 3 n (bac=0 or dci=1) (bac=1 & dci=0) cnt 3 6 (cnt 3 2&d=0) & [bac = 1 or (bac = 0 & cnt < n)] 1) setting dci = 1 causes e = d 2) setting a/b = 0 causes e = d bac=0or dci=1 local access wait for start flag s/g = 0 e=d cnt = 6 bac = d.c. dci = d.c. local access transmit / stop flag s/g = 0 e=d bac dci state s/g e in out pef 81912/81913 functional description data sheet 57 2001-03-30 1. local d-channel controller transmits upstream in the initial state (ready state) neither the local d-channel sources nor any of the terminals connected to the s-bus transmit in the d-channel. the q-smint ? ix s-transceiver thus receives bac = 1 (iom ? -2 du line) and transmits s/g = 1 (iom ? -2 dd line). the access will then be established according to the following procedure: ? local d-channel source verifies that bac bit is set to one (currently no bus access). ? local d-channel source issues tic bus address and verifies that no controller with higher priority requests transmission (tic bus access must always be performed even if no other d-channel sources are connected to iom ? -2). ? local d-channel source issues bac = 0 to block other sources on iom ? -2 and to announce d-channel access. ? q-smint ? ix s-transceiver pulls s/g bit to zero (local access state) as soon as cnt 3 n (see note) to allow sending d-channel data from the entitled source. q-smint ? ix s-transceiver transmits inverted echo channel (e bits) on the s-bus to block all connected s-bus terminals (e = d ). ? local d-channel source commences with d data transmission on iom ? -2 as long as it receives s/g = 0. ? after d-channel data transmission is completed the controller sets the bac bit to one. ? q-smint ? ix s-transceiver transmits non-inverted echo (e = d). ? q-smint ? ix s-transceiver pulls s/g bit to one (ready state) to block the d-channel controller on iom ? -2. note: if right after d-data transmission the d-channel arbiter goes to state ready and the local d-channel source wants to transmit again, then it may happen that the leading 0 of the start flag is written into the d-channel before the d-channel source recognizes that the s/g bit is pulled to 1 and stops transmission. in order to prevent unintended transitions to state s-access, the additional condition cnt 3 2 is introduced. as soon as cnt 3 n, the s/g bit is set to 0 and the d-channel source may start transmission again (if tic bus is occupied). this allows an equal access for d-channel sources on iom ? -2 and on the s interface. 2. terminal transmits d-channel data upstream the initial state is identical to that described in the last paragraph. when one of the connected s-bus terminals needs to transmit in the d-channel, access is established according to the following procedure: ? s-transceiver recognizes that the d-channel on the s-bus is active via d = 0. ? s-transceiver transfers s-bus d-channel data transparently through to the upstream iom ? -2 bus. pef 81912/81913 functional description data sheet 58 2001-03-30 2.3.6 activation/deactivation of iom ? -2 interface the deactivation procedure of the iom ? -2 interface is shown in figure 30. after detecting the code di (deactivation indication) the q-smint ? ix responds by transmitting dc (deactivation confirmation) during subsequent frames and stops the timing signals after the fourth frame. the clocks stop at the end of the c/i-code in iom ? - 2 channel 0. ? figure 30 deactivation of the iom ? -2 clocks conditions for power-down if none of the following conditions is true, the iom ? -2 interface can be switched off, reducing power consumption to a minimum. ? s-transceiver is not in state deactivated ? signal info0 on the s-interface ? uk0-transceiver is not in state deactivated ? pin du is low (either at the iom ? -2 interface or via iom_cr.spu) ? external pin eaw external awake is low ? bit mode 1.cfs = 0 ? stop on the correct place in the iom ? -2 frame. dcl must be low during power down (stop on falling edge of dcl) (see figure 30 ). itd10292 di di di di di di fsc din dout dc dc dc dc dr dr detail see fig.b din dcl dc/ ii / c i / c i / c deactivated deactivated a) b) r iom -2 interface iom -2 interface r pef 81912/81913 functional description data sheet 59 2001-03-30 a deactivated iom ? -2 can be reactivated by one of the following methods: ? pulling pin du line low: C directly at the iom ? -2 interface C via the p interface with "software power up" (iom_cr:spu bit) ? pulling pin eaw external awake low ? setting configuration select mode1:cfs bit = 0 ? level detection at the s-interface ? activation from the u-interface pef 81912/81913 functional description data sheet 60 2001-03-30 2.4 u-transceiver the state machine of the u-transceiver is based on the nt state machine in the peb / pef 8191 documentation [12]. note: self test request and self test passed are not executed by the u-transceiver the u-transceiver is configured and controlled via the registers described in chapter 4.11 . the u-transceiver is always in iom ? -2 channel 0. it is possible to select between a state machine that simplifies programming (see chapter 2.4.10.6 ) and the state machine as known from the peb / pef 8091 (see chapter 2.4.10.2 ). 2.4.1 2b1q frame structure transmission on the u 2b1q -interface is performed at a rate of 80 kbaud. the code used is reducing two bits to one quaternary symbol (2b1q). data is grouped together into u-superframes of 12 ms each. each superframe consists of eight basic frames which begin with a synchronization word and contain 222 bits of information. the first basic frame of a superframe starts with an inverted synchword (isw) compared to the other basic frames (sw). the structure of one u-superframe is illustrated in figure 31 and figure 32 . figure 31 u-superframe structure ? figure 32 u-basic frame structure out of the 222 information bits 216 contain 2b + d data from 12 iom ? -frames, the remaining 6 bits are used to transmit maintenance information. thus 48 maintenance bits are available per u-superframe. they are used to transmit two eoc-messages (24 bit), 12 maintenance (overhead) bits and one checksum (12 bit). isw 1. basic frame sw 2. basic frame . . . sw 8. basic frame <---12 ms---> ? (i) sw (inverted) synch word 18 bit (9 quat) 12 2b + d user data 216 bits (108 quat) m1 C m6 maintenance data 6 bits (3 quat) <---1,5 ms---> pef 81912/81913 functional description data sheet 61 2001-03-30 ? C isw inverted synchronization word (quad): C 3 C 3 + 3 + 3 + 3 C 3 + 3 C 3 C 3 C sw synchronization word (quad): + 3 + 3 C 3 C 3 C 3 + 3 C 3 + 3 + 3 C crc cyclic redundancy check C eoc embedded operation channel a = address bit d/m = data / message bit i = information (data / message) C act activation bit act = (1) C> layer 2 ready for communication table 15 u-superframe format fram- ing 2b + d overhead bits (m1 C m6) quat position s 1 C 9 10 C 117 118 s 118 m 119 s 119 m 120 s 120 m bit position s 1 C 18 19 C 234 235 236 237 238 239 240 super frame # basic frame # sync word 2b + d m1 m2 m3 m4 m5 m6 1 1 isw 2b + d eoc a1 eoc a2 eoc a3 act/ act 11 2 sw 2b + d eoc dm eoc i1 eoc i2 dea / ps1 1 febe 3 sw 2b + d eoc i3 eoc i4 eoc i5 sco/ ps2 crc1 crc2 4 sw 2b + d eoc i6 eoc i7 eoc i8 1/ ntm crc3 crc4 5 sw 2b + d eoc a1 eoc a2 eoc a3 1/ cso crc5 crc6 6 sw 2b + d eoc dm eoc i1 eoc i2 1 crc7 crc8 7 sw 2b + d eoc i3 eoc i4 eoc i5 uoa / sai crc9 crc 10 8 sw 2b + d eoc i6 eoc i7 eoc i8 aib / nib crc 11 crc 12 2,3 lt- to nt dir. > / < nt- to lt dir. pef 81912/81913 functional description data sheet 62 2001-03-30 C dea deactivation bit dea = (0) C> lt informs nt that it will turn off C cso cold start only cso = (1) C> nt-activation with cold start only C uoa u-only activation uoa = (0) C> u-only activated C sai s-activity indicator sai = (0) C> s-interface is deactivated C febe far-end block error febe = (0) C> far-end block error occurred C ps1 power status primary source ps1 = (1) C> primary power supply ok C ps2 power status secondary source ps2 = (1) C> secondary power supply ok C ntm nt-test mode ntm = (0) C> nt busy in test mode C aib alarm indication bit aib = (0) C> interruption (according to ansi) C nib network indication bit nib = (1) C> no function (reserved for network use) C sco start on command only bit C 1 (currently not defined by ansi/etsi) can be accessed by the system interface for proprietary use the principle signal flow is depicted in figure 33 and figure 34 . the data is first grouped in bits that are covered by the crc and bits that are not. after the crc generation the bits are arranged in the proper sequence according to the 2b1q frame format, encoded and finally transmitted. in receive direction the data is first decoded, descrambled, deframed and handed over for further processing. ? figure 33 u 2b1q framer - data flow scheme scrambler sync/inv. sync tone/pulse patterns m u x 2b1q encoding m u x crc generation m1,2,3 (eoc) m5,6 except crc 2b+d m4 u 2b1q -fram er ( m- bit handling acc. t o etr080) control m u x m u x ufr amer .emf 2b+d, m4 pef 81912/81913 functional description data sheet 63 2001-03-30 ? figure 34 u 2b1q deframer - data flow scheme 2.4.2 maintenance channel the last three symbols (6 bits) of each basic frame are used as m (maintenance)- channel for the exchange of operation and maintenance data between the network and the nt. approved m-bit data is first processed and then reported to the c by interrupt requests. the verification method is programmed in the mfilt register (see chapter 4.11.2 ). eoc-data is inserted into the u-frame at the positions m1, m2 and m3 ( table 15 ) thereby permitting the transmission of two complete eoc-messages (2 12 bits) within one u-superframe (see chapter 2.4.3 ). m4 bits are used to communicate status and maintenance functions between the transceivers. the meaning of a bit position is dependent upon the direction of transmission (upstream/downstream) and the operation mode (nt/lt). see table 15 for the different meaning of the m4 bits. for details see chapter 2.4.4 . the m5 and m6 bits contain the febe bit and the crc bits. for details see chapter 2.4.6 . 2.4.2.1 reporting to the c interface the maintenance channel information is exchanged with external devices via the appropriate registers. received maintenance channel information is reported to the c by an interrupt. d e m u x m1,2,3 (eoc) m5,6 except crc 2b+d m4 u 2b1q -deframer (m-bit handling acc. to etr080) control descrambler d e m u x crc check 2b1q decoding sync/inv. sync d e m u x udeframer.emf pef 81912/81913 functional description data sheet 64 2001-03-30 2.4.2.2 access from the c interface the maintenance data to be transmitted can be programmed by writing the internal eocw/m4w/m56w registers. 2.4.2.3 availability of maintenance channel information transmission of the maintenance channel data is only possible if a superframe is transmitted and the m-bits are transparent (m-bits are normal in table 25 ). in other states all maintenance bits are clamped to high. reception of the maintenance channel data is enabled by the state machine in the following states: reporting and execution of maintenance information is only sensible if the q-smint ? ix is synchronous. filters are provided to avoid meaningless reporting. reset values are applied to the maintenance bits before the state machine enters one of the states in table 16 . 2.4.2.4 m-bit register access timing since the maintenance data must be put into and read from the u-frame in time there is the need for synchronization if m-bit data is exchanged via the c-interface. below the timing is given for the access to the m-bit read and write registers. the write access timing is depicted in figure 35 . timing references for a write access are the 6 ms and 12 ms interrupts which are accommodated in the istau register. an active 6 ms interrupt signals that from this event there is a time frame of 3 basic frames duration (4.5 ms) for the write access to the eocw register. the 12 ms interrupt serves as time reference for the write access to the m4w and m56w registers. from the point of time the 12 ms interrupt goes active there is a time window of 7 basic frames to overwrite the register values. the programmed data will be sent out with the next u-superframe. table 16 enabling the maintenance channel (receive direction) synchronized1 synchronized2 wait for act transparent error s/t pend. deac. s/t pend. deac. u analog loop back pef 81912/81913 functional description data sheet 65 2001-03-30 note that the point of time when the 6 ms and 12 ms interrupts are generated within basic frame #1 and #5 is not fixed and may vary. ? figure 35 write access timing the read access timing is illustrated in figure 36 . an interrupt source of the same name is associated with each read register (eocr, m4r, m56r). an eoc interrupt indicates that the value of the eocr register has been changed and updated. so do the m4 and m56 interrupts. note that unlike the 6 ms and 12 ms interrupts the read interrupts are only generated on change of the register value and do not occur periodically. the eoc, m4 and m56 interrupt bits are all accommodated in the istau register. #1 #5 #4 #8 c write access time to eocw max. 3 base frames (4.5ms) 6ms interrupt frame no. #1 1. eoc 2. eoc 3baseframes (4.5ms) c write access time to eocw #1 #1 c write access time to m4w, m56w max. 7 base frames (10.5ms) 12ms interrupt frame no. #8 read access to istau clears 6ms interrupt read access to istau clears 12ms interrupt wr_acs_timg_qsmint.emf pef 81912/81913 functional description data sheet 66 2001-03-30 ? figure 36 read access timing 2.4.3 processing of the eoc 2.4.3.1 eoc commands the eoc command consists of an address field, a data/message indicator and an eight- bit information field. with the address field the destination of the transmitted message/ data is defined. addresses are defined for the nt, 6 repeater stations and broadcasting. #1 #5 #4 #8 c read access time to eocr max.3baseframes (4.5ms) eoc interrupt frame no. #1 1. eoc 2. eoc 3 base frames (4.5ms) c read access time to eocr #1 #1 c read access time to m4r max. 7 base frames (10.5ms) m4 interrupt frame no. #8 #1 #1 c read access time to m56r max. 7 base frames (10.5ms) m56 interrupt frame no. #8 set active in frame #1 if value has been updated set active in frame #1 if value has been updated set active in frame #1 or #5 if value has been updated read access to istau clears eoc interrupt read access to istau clears m4 interrupt read access to istau clears m56 interrupt wr_acs_timg_qsmint.emf pef 81912/81913 functional description data sheet 67 2001-03-30 the data/message indicator needs to be set to (1) to indicate that the information field contains a message. if set to (0), numerical data is transferred to the nt. currently no numerical data transfer to or from the nt is required. ? ? table 17 coding of eoc-commands eoc address field data/ message indicator information o (rigin) d (estination) message a1a2a3 d/m i1 i2 i3 i4 i5 i6 i7 i8 lt nt 0 0 0 x nt 111 x broadcast 0 01 1 10 x repeater stations no. 1 C no. 6 0 data 1 message 1 01010000 o d lbbd 1 01010001 o d lb1 1 01010010 o d lb2 1 01010011 o d rcc 1 01010100 o d ncc 1 11111111 o d rtn 1 00000000 d/o o/d h 1 10101010 d o utc table 18 usage of supported eoc-commands hex- code function i1-i8 d u 00 h h hold . provokes no change. the device issues hold if no nt or broadcast address is used or if the d/m indicator is set to (0). 50 lbbd close complete loop-back (b1, b2, d) . if this command is detected in nt eoc auto mode the c/i-code arl is issued by the q-smint ? ix u-transceiver. pef 81912/81913 functional description data sheet 68 2001-03-30 2.4.3.2 eoc processor the on-chip eoc-processor is responsible for the correct insertion and extraction of eoc-data on the u-interface. the eoc-processor can be programmed either to auto mode or to transparent modes (see chapter 2.4.3.3 ). figure 37 shows the registers and pins that are involved when eoc data is transmitted and received. 51 lb1 closes b1 loop-back in nt . all b1-channel data will be looped back within the q-smint ? ix u-transceiver. the bits lb1 and u/iom ? are set in the register loop. 52 lb2 closes b2 loop-back in nt . all b2-channel data will be looped back within the q-smint ? ix u-transceiver. the bits lb2 and u/iom ? are set in the register loop. 53 rcc request corrupt crc . upon receipt the q-smint ? ix transmits corrupted (= inverted) crcs upstream. this allows to test the near end block error counter on the lt-side. the far end block error counter at the q-smint ? ix-side is stopped and q-smint ? ix-error indications are retained. 54 ncc notify of corrupt crc . upon receipt of ncc the q- smint ? ix-block error counters (near-end only) are disabled and error indications are retained. this prevents wrong error counts while corrupted crcs are sent. aa utc unable to comply . message sent instead of an acknowledgment if an undefined eoc-command or d/m bit=0 was received by the q-smint ? ix. ff rtn return to normal . with this command all previously sent eoc-commands will be released. the eocw register is reset to its initial state (ff h ). xx ack acknowledge . if a defined and correctly addressed eoc- command was received by the q-smint ? ix, the q-smint ? ix replies by echoing back the received command. table 18 usage of supported eoc-commands (contd) hex- code function i1-i8 d u pef 81912/81913 functional description data sheet 69 2001-03-30 ? figure 37 eoc message reception ? figure 38 eoc command/message transmission eocr register last verified eoc message eoc message filtering mfilt.eoc eoc processor interrupt controller int u receive superframe echo eoc_rx.emf eocw eoc command/ message u transmit superframe eoc_tx.emf eoc processor u-rx frame every 6 msec eoc auto= '1' enable c pef 81912/81913 functional description data sheet 70 2001-03-30 2.4.3.3 eoc operating modes the eoc operating modes are programmable in the mfilt register (see chapter 4.11.2 ) eoc auto mode C acknowledgement: all received eoc-frames are echoed back to the exchange immediately without triple-last-look. if an address other than (000) b or (111) b is received, a hold message with address (000) b is returned. however there is an exception: the q-smint ? ix will send a utc after three consecutive receptions of d/ m = 0 or after an undefined command. C latching: all detected eoc-commands, i.e. lbbd, rcc etc., are latched. multiple subsequent valid eoc-commands are executed in parallel, as long as they are not disabled with the eoc rtn command or a deactivation. C reporting: with the triple-last-look criterion fulfilled the new eoc-command will be reported by an interrupt, independently of the address used and the status of the d/m indicator. the triple last look criterion implies that the new verified message is different to the last tll-verified message. C execution: the eoc-commands listed in table 17 will be executed automatically by the u-transceiver if they were addressed correctly (000 b or 111 b ) and the d/m bit was set to message (1). the execution of a command is performed only after the triple- last-look criterion is met. eoc transparent mode 6 ms C acknowledgement: there is no automatic acknowledgement in transparent mode. therefore the external c has to perform the eoc-procedure. 2 msec must be available for the report and the subsequent access of the transmit eoc data of the next outgoing eoc-frame. C latching: no latching is performed due to no execution. C reporting: the received eoc-frame is reported to the c by an interrupt every 6 ms. verification, acknowledgment and execution of the received command have to be initiated by an external controller. the c can program back all defined test functions (close/open loops, send corrupted crcs). in the transmit direction, the last written eoc-code from the c is used. C execution: no automatic execution in transparent modes. the appropriate actions can be programmed by the c. transparent mode with on change bit active C acknowledgment: there is no automatic acknowledgement in transparent mode. for details see above. C latching: no latching is performed due to no execution. pef 81912/81913 functional description data sheet 71 2001-03-30 C reporting: this mode is almost identical to the transparent mode 6 ms. but a report to the c by an interrupt takes place only, if a change in the eoc message has been detected. C execution: no automatic execution in transparent modes. the appropriate actions can be programmed by the c. transparent mode with tll active C acknowledgement: there is no automatic acknowledgment in transparent mode. for details see above. C latching: no latching is performed due to no execution. C reporting: this mode is almost identical to the transparent mode 6 ms. but a report to the c by an interrupt takes place only, if the new eoc command has been detected in at least three consecutive eoc messages. C execution: no automatic execution in transparent modes. the appropriate actions can be programmed by the c. 2.4.3.4 examples for different eoc modes general in the following examples some letters like a,b,c are used to symbolize eoc command. there are also particular eoc commands mentioned which indicate special system behavior (e.g. utc, h). the examples are shown in tables. pef 81912/81913 functional description data sheet 72 2001-03-30 eoc automode ? a, b: eoc commands with correct address, d/m bit = 1 and defined command. ? c: eoc command with wrong address. immediately acknowledged with h. ? d: eoc command which is not defined or d/m bit = 0. acknowledgement after tll with utc. table 19 eoc auto mode remarks immediately akcn. immediately akcn. no report to system interface wrong address -> h undef. command or d/m=0 input from c access to eocw register has direct impact on eoc tx. eoc tx aaabaaa hhhdd utc utc add utc eoc rx a a ab a a a c c c d d dda d d d report to c a c d d pef 81912/81913 functional description data sheet 73 2001-03-30 transparent mode 6 ms) transparent mode @change transparent mode tll table 20 transparent mode 6 ms remarks input from c a b c d eoc tx aaaabbbcccddd eoc rx cabccaaaabbbb report to c c a b c c aaaabbbb table 21 transparent mode @change remarks input from c a b c d eoc tx a aaabbbccccdd eoc rx cabccaaaaabbb report to c a b c a b table 22 transparent mode tll remarks saturation single eoc b interrupts tll saturnation input from c a b c d eoc tx aaaabbbbb ccccdddd eoc rx c c ccc a a ab a a a b b bbb report to c c a a b pef 81912/81913 functional description data sheet 74 2001-03-30 2.4.4 processing of the overhead bits m4, m5, m6 2.4.4.1 m4 bit reporting to the c four different validation modes can be selected and take effect on a per bit base . only if the received m4 bit change has been approved by the programmed filter algorithm a report to the c is triggered. the following filter algorithms are provided and can be programmed in the mfilt register: ? on change ? triple-last-look (tll) coverage ? crc coverage note that unlike the m4 bits the m56 bits are not included in the crc generation! ? crc and tll coverage 2.4.4.2 m4 bit reporting to state machine some m4 bits, act, dea and uoa, have two destinations, the state machine and the c. regarding these bits triple-last-look (tll) is applied by default before the changed status is input to the state machine. via the mfilt register the user can decide whether the m4 bits which are input to the state machine shall be approved ? by tll (default setting, since tll is a bellcore requirement) or ? by the same verification mode as selected for reporting to the c. the reset values before activation are act=0, dea=1, uoa=0. 2.4.4.3 m5, m6 bit reporting to the c by default changes in the received spare bits m51, m52, and m61 are reported to the c only if no crc violation has been detected. however the user has the choice to program one of the following two options in the mfilt register (for details see chapter 4.11.2 ): ? same validation algorithm is applied to m5 and m6 bits as programmed for m4 bits ? on change in transmit direction these bits are set by default to 1 if they are not explicitly set by an c access (via m56w register). 2.4.4.4 summary of m4, m5, m6 bit reporting figure 39 summarizes again the various filtering options that are provided for the several maintenance channel bits. pef 81912/81913 functional description data sheet 75 2001-03-30 ? figure 39 maintenance channel filtering options figure 40 illustrates the point of time when a detected m4, m5, m6 bit change is reported to the c and when it is reported to the state machine: ? towards the c reports are always sent after one complete u-superframe was received, ? whereas towards the state machine m4-bit changes (act, dea, uoa, sai) are instantly passed on as soon as they were approved. in context of figure 40 this means that a verified act bit change is already reported at the end of basic frame #1 instead of the end of basic frame #8. ? figure 40 m4 bit report timing (statemachine vs. c) m4 tll & on change m u x m u x state machine mfilt.eoc(bit3,2,1) mfilt.m4(bit5) m456_filter_qsmint.emf m u x mfilt.m4(bit4,3) crc m5, m6 tll & on change m u x crc mfilt.m56(bit6) m56 int m4 int sw 2b+d m1-6 isw 2b+d m1-6 sw 2b+d m1-6 isw 2b+d m1-6 8. basic frame 2. basic frame 1. basic frame n. super frame n+1. super frame reported to state machine e.g. act bit validated m4tim2sm_qsmint.emf m4= act time int pef 81912/81913 functional description data sheet 76 2001-03-30 however, if the same filter is selected towards the state machine as programmed towards the c, the user has to be aware that if crc mode is active, the state machine is informed at the end of the next u-superframe. 2.4.5 m4, m5, m6 bit control mechanisms figure 41 and figure 42 show the control mechanisms that are provided for m4, m5 and m6 bit data: via the m4wmask register the user can selectively program which m4 bits are externally controlled and which are set by the internal state machine or dedicated pins (ps1, ps2). if one m4wmask bit is set to 0 then the m4 bit value in the u-transmit frame is determined by the bit value at the corresponding bit position in the m4w register. note: by bit 6 in the m4wmask register it can be selected whether sai is set by the state machine or by c access and whether the value of the received uoa bit is reported to the state machine or uoa= 1 is signalled. via the m4rmask register the user can selectively program which m4 bit changes shall cause an report to the c. the m4w register latches the m4 bits that are sent with the next available u-superframe. the m4r register contains the last validated m4 bit data. the default value of m51, m52 and m61 can be overwritten at any time by use of register m56w . m56r latches the last received and verified m5, m6 bit data. the control of the febe bit is performed by the crc-processor, see chapter 2.4.6 . pef 81912/81913 functional description data sheet 77 2001-03-30 ? figure 41 m4, m5, m6 bit control in receive direction ? figure 42 m4, m5, m6 bit control in transmit direction m4r register aib uoa m46 m45 m44 sco dea act m56r register 0 ms2 ms1 m61 m52 m51 u receive superframe m4 filtering (per bit) m56 filtering (per bit) mfilt.m4 mfilt.m56 en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis state machine mux '1' interrupt controller int nebe febe uoa dea act dea uoa act m4rmask '0'= enabled '1'= disabled m4wmask.bit6 m456_nt_rx_qsmint. e state machine m4w register nib sai m46 cso ntm ps2 ps1 act mux c/i codes act sai mux m4wmask mux mux mux mux mux mux '1' '1' u transmit superframe m56w register 1 1 1 1 m61 m52 m51 febe mux nebe counter opmode.febe ps2 ps1 pins '1'= m4w reg. '0'= sm/ pin c c m4wmask.bit6 m456_nt_tx_qsmint.emf '1' '0' pef 81912/81913 functional description data sheet 78 2001-03-30 2.4.6 cyclic redundancy check / febe bit an error monitoring function is implemented covering the 2b + d and m4 data transmission of a u-superframe by a cyclic redundancy check (crc). the computed polynomial is: g (u) = u 12 + u 11 + u 3 + u 2 + u + 1 (+ modulo 2 addition) the check digits (crc bits crc1, crc2, , crc12) generated are transmitted in the u-superframe. the receiver will compute the crc of the received 2b + d and m4 data and compare it with the received crc-bits generated by the transmitter. a crc-error will be indicated to both sides of the u-interface, as a nebe (near-end block error) on the side where the error is detected, as a febe (far-end block error) on the remote side. the febe-bit will be placed in the next available u-superframe transmitted to the originator. figure 43 illustrates the crc-process. pef 81912/81913 functional description data sheet 79 2001-03-30 ? figure 43 crc-process g(u) =? nebe error counter febe error counter nebe error counter =? febe error counter g(u) crc 1... crc 12 crc 1... crc 12 crc1... crc12 crc1... crc12 (2b + d), m4 du g(u) g(u) (mon-8) du dd iom ? -2 nt u lt dd (mon-8) febe = "0" sfr(n + 2) febe = "1" sfr(n + 2) sfr(n + 1.0625) sfr(n + 0.0625) sfr(n + 1.0625) febe = "0" sfr(n + 1.0625)* febe = "1" sfr(n + 1) sfr(n) (2b + d), m4 no yes no yes iom ? -2 crcok=1 crcok=0 crcok=1 crcok=0 *0.0625 of a sfr is the 60 quats offset of the nt transmit data. c access int c access int crc_qsmint.emf pef 81912/81913 functional description data sheet 80 2001-03-30 2.4.7 block error counters the u-transceiver provides internal counters for far-end and near-end block errors. this allows a comfortable surveillance of the transmission quality at the u-interface. in addition, the occurrence of near-end errors, far-end errors, and the simultaneous occurrence of both errors are reported to the c by an interrupt at the beginning of the following receive-superframe. a block error is detected each time when the calculated checksum (crc) of the received data does not correspond to the control checksum transmitted in the successive superframe. one block error thus indicates that one u-superframe has not been transmitted correctly. no conclusion with respect to the number of bit errors is therefore possible. 2.4.7.1 near-end and far-end block error counter a near-end block error (nebe) indicates that the error has been detected in the receive direction (i.e. nebe in the nt = lt => nt error). each detected nebe-error increments the 8-bit nebe-counter. when reaching the maximum count, counting is stopped and the counter value reads (ff h ). a far-end block error identifies errors in transmission direction (i.e. febe in the nt = nt => lt-error). febe errors are processed in the same manner as nebe-errors. the febe and nebe counter values can be read in registers febe and nebe. the counter is cleared after read. the counters are also reset to 00 h in all states except the states listed in table 16 . 2.4.7.2 testing block error counters figure 44 illustrates how near- and far-end block error counters can be tested. transmission errors are simulated with artificially corrupted crcs. with two commands the cyclic redundancy checksum can be inverted in the upstream and downstream direction. a third command offers to invert single febe-bits. ? eoc command ncc: requests the q-smint ? ix to notify corrupted crcs. the functional behavior of the q-smint ? ix and the nebe-counter depends on the mode selected: C eoc auto mode: nebe-detection stopped: no nebe interrupt generated and nebe-counter disabled C eoc transparent mode nebe-detection enabled: nebe interrupt generated and nebe-counter enabled ? eoc command rcc: requests the q-smint ? ix to send corrupt crcs. after issuing rcc near-end block errors will be registered on the lt-side. pef 81912/81913 functional description data sheet 81 2001-03-30 the functional behavior of the q-smint ? ix and the febe-counter depends on the mode selected: C eoc auto mode: the q-smint ? ix will react with a permanently inverted upstream crc. febe-detection stopped: no febe interrupt generated and febe-counter disabled C eoc transparent mode the external c must react on rcc by programming test.ccrc = 1. febe-detection enabled: febe interrupt generated and febe-counter enabled ? eoc command rtn: disables all previously sent eoc commands. ? m56w.febe by setting / resetting m56w.febe (m56w.febe can only be set and controlled externally if opmode.febe is set to 1), the febe bit of the next available u-frame can be set / reset . therefore, it is possible to predict exactly the febe-counter value. pef 81912/81913 functional description data sheet 82 2001-03-30 ? figure 44 block error counter test 2.4.8 scrambling/ descrambling the scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are transmitted. the scrambling / descrambling process is controlled fully by the q- smint ? ix . hence, no influence can be taken by the user. 2.4.9 c/i codes the operational status of the u-transceiver is controlled by the control/indicate channel (c/i-channel). lt u transparent auto-mode eoc : ncc (mon-0) ncc (mon-0) ack stop error detect eoc acknowledge iom a -2 start inverse crc bits (mon-8) ccrc error count nebe febe = "0" (mon-8) rbef error count nebe end inverse crc bits (mon-8) norm eoc : rtn eoc acknowledge (mon-0) ack free error detect eoc : rcc (mon-0) rcc stop error detect eoc acknowledge (mon-0) ack start inverse crc bits error count febe febe = "0" (mon-8) rben eoc : rtn (mon-0) rtn free error detect eoc acknowledge end inverse crc bits (mon-0) rtn error count febe (mon-8) abec (mon-8) abec c interface istau.eoc=1 eocr = 'ncc' istau.febe/ nebe=1 test.ccrc = '1' istau.eoc=1 eocr = 'rtn' istau.eoc=1 eocr = 'rcc' istau.febe/ nebe=1 m56r.febe = '1' istau.eoc=1 eocr = 'rtn' test.ccrc = '0' m56r.nebe = '1' eoc eoc itd04226_qsmint.emf pef 81912/81913 functional description data sheet 83 2001-03-30 table 23 presents all defined c/i codes. a new command or indication will be recognized as valid after it has been detected in two successive iom ? -2-frames (double last-look criterion). note: unconditional c/i-commands must be applied for at least 4 iom ? -2 frames for reliable recognition by the u-transceiver. commands have to be applied continuously on du until the command is validated by the u-transceiver and the desired action has been initiated. afterwards the command may be changed. an indication is issued permanently by the u-transceiver on dd until a new indication needs to be forwarded. because a number of states issue identical indications it is not possible to identify every state individually. ? ai: activation indication ail: activation indication loop ar: activation request arl: activation request local loop table 23 u - transceiver c/i codes code in out 0000 tim dr 0001 res C 0010 C C 0011 C C 0100 ei1 ei1 0101 ssp C 0110 dt C 0111 C pu 1000 ar ar 1001 C C 1010 arl arl 1011 C C 1100 ai ai 1101 C C 1110 C ail 1111 di dc pef 81912/81913 functional description data sheet 84 2001-03-30 dc: deactivation confirmation di: deactivation indication dr: deactivation request dt: data through test mode ei1: error indication 1 pu: power-up res: reset ssp: send single pulses test mode tim: timing request 2.4.10 state machines for line activation / deactivation 2.4.10.1 notation the state machines control the sequence of signals at the u-interface that are generated during the start-up procedure. the informations contained in the following state diagrams are: C state name C u-signal transmitted C overhead bits transmitted C c/i-code transmitted C transition criteria C timers figure 45 shows how to interpret the state diagrams. ? figure 45 explanation of state diagram notation state name signal transmitted to u-interface (general) single bit transmitted to u-interface indication transmitted on c/i-channel (dout) in out itd04257.vsd pef 81912/81913 functional description data sheet 85 2001-03-30 combinations of transition criteria are possible. logical and is indicated by & (tn & dc), logical or is written or and for a negation / is used. the start of a timer is indicated with txs (x being equivalent to the timer number). timers are always started when entering the new state. the action resulting after a timer has expired is indicated by the path labelled txe. pef 81912/81913 functional description data sheet 86 2001-03-30 2.4.10.2 standard nt state machine (iec-q / ntc-q compatible) ? figure 46 standard nt state machine (iec-q / ntc-q compatible) (footnotes: see dependence of outputs on page 91 ) sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e&di lsuor(/lof&t13e) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu pef 81912/81913 functional description data sheet 87 2001-03-30 note: the test modes data through (dt) and send single pulses (ssp) are invoked via c/i codes dt and ssp according to table 23 . setting sres.res_u to 1 forces the u-transceiver into test mode quiet mode (qm), i.e. the u-transceiver is hardware reset. if the metallic loop termination is used, then the u-transceiver is forced into the states reset and transparent by valid pulse streams on pin mti according to table 30 . note: if the state machine is in state deactivated and the iom ? -2 clocks are not running, then the transitions to iom ? -2 awaked or alerting can be invoked by writing directly the corresponding c/i-code to register uciw via the c interface. 2.4.10.3 inputs to the u-transceiver: c/i-commands: ai activation indication the downstream device issues this indication to announce that its layer-1 is available. the u-transceiver informs the lt side by setting the act bit to 1. ar activation request the u-transceiver is requested to start the activation process by sending the wake- up signal tn. arl activation request local loop-back the u-transceiver is requested to operate an analog loop-back (close to the u- interface) and to begin the start-up sequence by sending sn1 (without starting timer t1). this command may be issued only after the u-transceiver has been hw- or sw- reset. this eases that the ec- and eq-coefficient updating algorithms converge correctly. the arl-command has to be issued continuously as long as the loop-back is required. di deactivation indication this indication is used during a deactivation procedure to inform the u-transceiver that it may enter the deactivated (power-down) state. dt data through this unconditional command is used for test purposes only and forces the u- transceiver into the transparent state. ei1 error indication 1 the downstream device indicates an error condition (loss of frame alignment or loss of incoming signal). the u-transceiver informs the lt-side by setting the act-bit to 0 thus indicating that transparency has been lost. res reset unconditional command which resets the u-transceiver. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. pef 81912/81913 functional description data sheet 88 2001-03-30 tim timing the u-transceiver is requested to enter state iom ? -2 awaked. u-interface events: act = 0/1 act-bit received from lt-side. C act = 1 requests the u-transceiver to transmit transparently in both directions. in the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is synchronized. C act = 0 indicates that layer-2 functionality is not available. dea = 0/1 dea-bit received from the lt-side C dea = 0 informs the u-transceiver that a deactivation procedure has been started by the lt-side. C dea = 1 reflects the case when dea = 0 was detected by faults due to e.g. transmission errors and allows the u-transceiver to recover from this situation. uoa = 0/1 uoa-bit received from network side C uoa = 0 informs the u-transceiver that only the u-interface is to be activated. the s/t-interface must be deactivated. C uoa = 1 requests the s/t-interface (if present) to activate. timers the start of timers is indicated by txs, the expiry by txe. table 24 shows which timers are used: ? 2.4.10.4 outputs of the u-transceiver: the following signals and indications are issued on iom ? -2 (c/i-indications) and on the u-interface (predefined u-signals): table 24 timers used timer duration (ms) function state t1 15000 supervisor for start-up t7 40 hold time receive reset t11 9 tn-transmission alerting t12 5500 supervisor ec-converge ec-training t13 15000 frame synchronization pend. receive reset t14 0.5 hold time pend. timing t20 10 hold time wait for sf pef 81912/81913 functional description data sheet 89 2001-03-30 c/i-indications ai activation indication the u-transceiver has established transparency of transmission. the downstream device is requested to establish layer-1 functionality. ail activation indication loopback the u-transceiver has established transparency of transmission. the downstream device is requested to establish a loopback #2. ar activation request the downstream device is requested to start the activation procedure. arl activation request loop-back the u-transceiver has detected a loop-back 2 command in the eoc-channel and has established transparency of transmission in the direction iom ? -2 to u-interface. the downstream device is requested to start the activation procedure and to establish a loopback #2. dc deactivation confirmation idle code on the iom ? -2-interface. dr deactivation request the u-transceiver has detected a deactivation request command from the lt-side for a complete deactivation or a s/t only deactivation. the downstream device is requested to start the deactivation procedure. ei1 error indication 1 the u-transceiver has entered a failure condition caused by loss of framing on the u-interface or expiry of timer t1. signals on u-interface the signals snx, tn and sp transmitted on the u-interface are defined in table 25 . ? table 25 u-interface signals signal synch. word (sw) superframe (isw) 2b + d m-bits tn 1) 3 3 3 3 sn0 no signal no signal no signal no signal sn1 present absent 1 1 sn2 present absent 1 1 sn3 present present 1 normal sn3t present present normal normal test mode sp 2) test signal test signal test signal test signal pef 81912/81913 functional description data sheet 90 2001-03-30 note: 1) alternating 3 symbols at 10 khz. note: 2) 4 options for the test signal can be selected by register test: a 40 khz signal composed by alternating +/-3 or +/-1 transmit pulses. a series of single pulses spaced at intervals of 1.5 ms; either alternating +/-1 or +/-3 pulses can be selected. input signals of the state machine and related u-signals the table below summarizes the input signals that control the nt state machine and that are extracted from the u-interface signal sequences. ? lof loss of framing this condition is fulfilled if framing is lost for 573 ms. lsec loss of signal behind echo canceller internal signal which indicates that the echo canceller has converged lsu loss of signal on u-interface this signal indicates that a loss of signal level for a duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where the nt waits for a response (no signal level) from the lt- side. lsue loss of signal on u-interface - error condition after a loss of signal has been noticed, a 588 ms timer is started. when it has elapsed , the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the nt is not prepared to lose signal level i.e. the lt has stopped transmission because of loss of framing, an unsuccessful activation, or the transmission line is interrupted. fd frame detected sfd super frame detected bbd0 / bbd1 bbd0/1 detected these signals are set if either 1' (bbd1) or 0' (bbd0) were detected in 4 subsequent basic frames. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd0 corresponds to the received signal sl2 in case of a normal activation, bbd1 corresponds to the internally received signal sn3 in case of analog loop back. tl awake tone detected the u-transceiver is requested to start an activation procedure. pef 81912/81913 functional description data sheet 91 2001-03-30 signals on iom ? -2 the data (b+b+d) is set to all 1s in all states besides the states listed in table 16 . dependence of outputs ? outputs denoted with 1) in figure 46 : signal output on u k0 depends on the received eoc command and on the history of the state machine according to table 26 : ? ? outputs denoted with 2) in figure 46 : c/i-code output depends on received eoc-command lbbd according to table 27 : ? ? outputs denoted with 3) in figure 46 : in states pend. deact. s/t and pend. deact. u the act-bit output depends on its value in the previous state. ? the value of the issued sai-bit depends on the received c/i-code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity of the downstream device. ? if state alerting is entered from state deactivated, then c/i-code pu is issued, else c/i-code dc is issued. table 26 signal output on u k0 eoc command history of the state machine signal output on u k0 received lbbd no influence sn3t received no lbbd or rtn after an lbbd state transparent has not been reached previously during this activation procedure sn3 state transparent has been reached previously during this activation procedure sn3t table 27 c/i-code output eoc command synchroni zed 2 wait for act transparent error s/t received no lbbd or rtn after an lbbd ar ar ai ar received lbbd arl arl ail arl pef 81912/81913 functional description data sheet 92 2001-03-30 2.4.10.5 description of the nt-states the following states are used: alerting the wake-up signal tn is transmitted for a period of t11 either in response to a received wake-up signal tl or to start an activation procedure on the lt-side. alerting 1 alerting 1 state is entered when a wake-up tone was received in the receive reset state and the deactivation procedure on the nt-side was not yet finished. the transmission of wake-up tone tn is started. analog loop-back transparency is achieved in both directions of transmission. this state can be left by making use of any unconditional command. deactivated only in state deactivated the device may enter the power-down mode. ec training the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. ec-training 1 the ec-training 1 state is entered if transmission of signal sn1 has to be started and the deactivation procedure on the nt-side is not yet finished. ec-training al the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. eq-training the receiver waits for signal sl1 or sl2 to be able to update the agc, to recover the timing phase, to detect the synch-word (sw), and to update the eq-coefficients. pef 81912/81913 functional description data sheet 93 2001-03-30 error s/t the downstream device is in an error condition (ei1). the lt-side is informed by setting the act-bit to 0 (loss of transparency on the nt-side). iom ? -2-awaked the u-transceiver is deactivated, but may not enter the power-down mode. pending deactivation of s/t the u-transceiver has received the uoa-bit at zero after a complete activation of the s/ t-interface. the u-transceiver requests the downstream device to deactivate by issuing dr. pending deactivation of u-interface the u-transceiver waits for the receive signal level to be turned off (lsu) to start the deactivation procedure. pending receive reset the pending receive reset state is entered upon detection of loss of framing on the u-interface or expiry of timer t1. this failure condition is signalled to the lt-side by turning off the transmit level (sn0). the u-transceiver then waits for a response (no signal level lsu) from the lt-side. pending timing in the nt-mode the pending timing state assures that the c/i-channel code dc is issued four times before entering the deactivated state. receive reset in state receive reset a reset of the uk0-receiver is performed, except in case that state receive reset was entered from state pend. deact. u. timer t7 assures that no activation procedure is started from the nt-side for a minimum period of time of t7. this gives the lt a chance to activate the nt. reset in state reset a software-reset is performed. synchronized 1 state synchronized 1 is the fully active state of the u-transceiver, while the downstream device is deactivated. pef 81912/81913 functional description data sheet 94 2001-03-30 synchronized 2 in this state the u-transceiver has received uoa = 1. this is a request to activate the downstream device. test the test signal sp is issued as long as c/i=ssp is applied. for further details see table 25 . transparent this state is entered upon the detection of act = 1 received from the lt-side and corresponds to the fully active state. wait for act upon the receipt of ai, the nt waits for a response (act = 1) from the lt-side. wait for sf the signal sn2 is sent on the u-interface and the receiver waits for detection of the superframe. wait for sf al this state is entered in the case of an analog loop-back and allows the receiver to update the agc, to recover the timing phase, and to update the eq-coefficients. 2.4.10.6 simplified nt state machine as an alternative to the activation/deactivation state machine of the u-transceiver known from the iec-q [9], a more software friendly state machine can be selected. in the early days of isdn, the activation and deactivation procedure in a nt was completely determined by the u- and s-transceiver state machines without a microcontroller being necessary. intelligent nts or u-terminals require a microcontroller and software. in this case the software controls both the s-and the u-transceiver state machine. the simplified u-transceiver state machine was developed to better address the needs and requirements of software running on the microcontroller. the simplified state machine offers the following advantages: C the software can tell whether the iom ? -2 clocks are active or powered down via the received c/i code C from the received c/i code the software always knows, what it is expected to do and what options it has. the software does not have to backtrack older c/i codes. pef 81912/81913 functional description data sheet 95 2001-03-30 C unnecessary c/i changes at irrelevant state transitions are omitted, hence the number of interrupts is reduced. all advantages can be offered by the following minor changes to the existing state machine: ? table 28 changes to achieve simplified nt state machine change state standard nt state machine simplified nt state machine change of transmitted c/i -code alerting dc/pu pu ec-training dc pu eq-training dc pu wait for sf dc pu synchronized 1 dc pu pend. receive res. ei1 dr pend. deact. u. dc dr wait for sf al dc dr ec-training al dc dr all other states no changes changed state transition criteria alerting 1 to alerting di di or tim ec-training 1 to ec-training di di or tim pend. deact. s/t to synchron. 1 di di or tim all other transition criterias no changes new state transitions receive reset to iom ? -2 awaked none t7e & tim reset to iom ? -2 awaked none tim pef 81912/81913 functional description data sheet 96 2001-03-30 test to iom ? -2 awaked none tim not supported state transitions reset to alerting di & ntauto none all other transitions no changes table 28 changes to achieve simplified nt state machine (contd) change state standard nt state machine simplified nt state machine pef 81912/81913 functional description data sheet 97 2001-03-30 ? figure 47 simplified nt state machine sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al ar ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1&sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd lof t1s, t11s ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e&di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s tim pu pu pu pu pu or tim or tim dr t7e & tim dr dr dr t1s t11s pef 81912/81913 functional description data sheet 98 2001-03-30 ? 2.4.11 metallic loop termination for north american applications a maintenance controller according to ansi t1.601 section 6.5 is implemented. the maintenance pulse stream from the u-interface metallic loop termination circuit (mlt) is fed to pin mti, usually via an optocoupler. it is digitally filtered for 20 ms and decoded independently on the polarity by the maintenance controller according to table 30 . therefore, the maintenance controller is capable of detecting the dc and ac signaling format. the q-smint ? ix automatically sets the u- transceiver in the proper state and issues an interrupt. the state selected by the mlt is indicated via two bits. the q-smint ? ix reacts on a valid pulse stream independently of the current u- transceiver state. this includes the power-down state. table 29 appearance of the state machine to the software c/i ind. meaning options u- transp arent dr lt has decided to deactivate or activation was lost: C after an activation or C after an activation attempt or C after reset di tim acknowledge and give permission to turn off the clocks acknowledge, clocks will stay active no dc four iom ? -2 frames with c/i code dc are issued before permission to turn off the clocks tim ar any other c/i- code turn on clocks start u-activation no action, permission to turn off the clocks will be given no pu clocks are on; u-interface is not transparent but may be synchronous (e.g. u-only activation) any c/i- code no action, clocks will remain on no ar used during activation. u- interface is synchronous and is waiting for an ok from the downstream device ai accept that activation can continue, layer 2 of the downstream device is ready. then wait for ci/ indication ai no ai u-interface transparent -- ei1 or act=0 no action, transmit data report problem on downstream device yes pef 81912/81913 functional description data sheet 99 2001-03-30 a test mode is valid for 75 seconds. if during the 75 seconds a valid pulse sequence is detected the 75 s timer starts again. after expiry of the 75 s timer the mlt maintenance controller goes back to normal operation. ? figure 48 shows examples for pulse streams with inverse polarity selecting quiet mode. ? figure 48 pulse streams selecting quiet mode table 30 ansi maintenance controller states number of counted pulses ansi maintenance controller state u-transceiver state machine <= 5 ignored no impact 6 quiet mode transition to state reset start timer 75s 7 ignored no impact 8 insertion loss measurement transition to state transparent start timer 75s 9 ignored no impact 10 normal operation transition to state reset >= 11 ignored no impact mlt.vsd pin mti 1 1 5 4 3 26 3 500 ms 3 500 ms 0 pin mti 1 1 20 ms < t high < 500 ms 5 4 3 26 3 500 ms 3 500 ms 0 4ms pef 81912/81913 functional description data sheet 101 2001-03-30 ? figure 49 interrupt structure u-transceiver a1 a2 i8 aib uoa m46 m45 m44 sco dea act mlt ci febe/ nebe m56 m4 eoc 6ms 12ms mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 0 ms2 ms1 nebe m61 m52 m51 febe m56r m4r m4rmask mfilt opmode.mlt crc, tll, no filtering tll, chg, no filtering mfilt eocr istau masku 0 7 0 7 0 7 crc, tll, no filtering 15 0 11 + mfilt + reserved interr_u_q2.vsd u ista mask int ucir 0 7 c/i c/i c/i c/i 0 7 pef 81912/81913 functional description data sheet 102 2001-03-30 2.5 s-transceiver the s-transceiver offers the nt and lt-s mode state machines described in the users manual v3.4 [10]. the s-transceiver lies in iom ? -2 channel 1 (default) and is configured and controlled via the registers described in chapter 4.7 . the state machine is set to nt mode (default) but can be set to lt-s mode via register programming. the te mode (s-transceiver te mode, u-transceiver disabled) is not supported. 2.5.1 line coding, frame structure line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. ? figure 50 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 50 ). in the direction te ? nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt ? te and te ? nt) with all framing and maintenance bits. 011 code violation pef 81912/81913 functional description data sheet 103 2001-03-30 ? figure 51 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. C f framing bit f = (0b) ? identifies new frame (always positive pulse, always code violation) C l. d.c. balancing bit l. = (0b) ? number of binary zeros sent after the last l. bit was odd C d d-channel data bit signaling data specified by user C e d-channel echo bit e = d ? received e-bit is equal to transmitted d-bit Cf a auxiliary framing bit see section 6.3 in itu i.430 C n n = C b1 b1-channel data bit user data C b2 b2-channel data bit user data C a activation bit a = (0b) ? info 2 transmitted a = (1b) ? info 4 transmitted C s s-channel data bit s 1 channel data (see note below) C m multiframing bit m = (1b) ? start of new multi-frame f a pef 81912/81913 functional description data sheet 104 2001-03-30 2.5.2 s/q channels, multiframing according to itu recommendation i.430 a multi-frame provides extra layer-1 capacity in the te-to-nt direction through the use of an extra channel between the te and nt (q- channel). the q bits are defined to be the bits in the f a bit position. in the nt-to-te direction the s-channel bits are used for information transmission. the s- and q-channels are accessed via c by reading/writing the sqr or sqx bits in the s/q channel registers (sqrr, sqxr). table 31 shows the s and q bit positions within the multi-frame. table 31 s/q-bit position identification and multi-frame structure frame number nt-to-te f a bit position nt-to-te m bit nt-to-te s bit te-to-nt f a bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s11 s21 s31 s41 s51 q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s12 s22 s32 s42 s52 q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s13 s23 s33 s43 s53 q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s14 s24 s34 s44 s54 q4 zero zero zero zero 1 2 one zero one zero s11 s21 q1 zero pef 81912/81913 functional description data sheet 105 2001-03-30 the s-transceiver starts multiframing if sqxr1.mfen is set. after multi-frame synchronization has been established in the te, the q data will be inserted at the upstream (te ? nt) f a bit position by the te in each 5th s/t frame, the s data will be inserted at the downstream (nt ? te) s bit position in each 5th s/t frame (see table 31 ). access to s2-s5-channel is not supported. interrupt handling for multi-framing to trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (sqw) or if the received q-channel have changed (sqc). in both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). the start of a multiframe can not be synchronized to an external signal. 2.5.3 data transfer between iom ? -2 and s 0 in the state g3 (activated) or if the internal layer-1 statemachine is disabled and xinf of register s_cmd is programmed to 011 the b1, b2 and d bits are transferred transparently from the s/t to the iom ? -2 interface and vice versa. in all other states 1s are transmitted to the iom ? -2 interface. note: in intelligent nt or intelligent lt-s mode the d-channel access can be blocked by the iom ? -2 d-channel handler. 2.5.4 loopback 2 c/i commands arl and ail close the analog loop as close to the s-interface as possible. etsi refers to this loop under loopback 2. etsi requires, that b1, b2 and d channels have the same propagation delay when being looped back. the d-channel echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). the loop is transparent. note: after c/i-code ail has been recognized by the s-transceiver, zeros are looped back in the b and d-channels (du) for four frames. 2.5.5 control of s-transceiver / state machine the s-transceiver activation/ deactivation can be controlled by an internal statemachine via the iom ? -2 c/i-channel or by software via the m c interface directly. in the default state the internal layer-1 statemachine of the s-transceiver is used. by setting the l1sw bit in the s_conf0 register the internal statemachine can be disabled and the layer-1 transmit commands, which are normally generated by the internal statemachine can be written directly into the s_cmd register or the received status read out from the s_sta register, respectively. the s-transceiver layer-1 control flow is shown in figure 52 . pef 81912/81913 functional description data sheet 106 2001-03-30 ? figure 52 s-transceiver control the state diagram notation is given in figure 53 . the information contained in the state diagrams are: C state name C signal received from the line interface (info) C signal transmitted to the line interface (info) C c/i code received (commands) C c/i code transmitted (indications) C transition criteria the transition criteria are grouped into: C c/i commands C signals received from the line interface (infos) C reset iom-2 layer-1 control layer-1 state machine macro_14 transmit info transmitter receiver receive info command register for transmitter (s_cmd) status register of receiver (s_sta) c/i command c/i indication m c-interface disable internal statemachine (s_conf.l1sw) pef 81912/81913 functional description data sheet 107 2001-03-30 ? figure 53 state diagram notation as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a * stands for a logical and combination. and a + indicates a logical or combination. test signals ? 2 khz single pulses (tm1) one pulse with a width of one bit period per frame with alternating polarity. ? 96 khz continuous pulses (tm2) continuous pulses with a pulse width of one bit period. note: the test signals tm1 and tm2 are invoked via c/i codes tm1 and tm2 according to chapter 2.5.5.1 . external layer-1 statemachine instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. the internal layer-1 statemachine can be disabled by setting the l1sw bit in the s_conf0 register to 1. the transmitter is completely under control of the microcontroller via register s_cmd. the status of the receiver is stored in register s_sta and has to be evaluated by the microcontroller. this register is updated continuously. if not masked a ric interrupt is generated by any change of the register contents. the interrupt is cleared after a read access to this register. reset states after an active signal on the reset pin rst the s-transceiver state machine is in the reset state. iom-2 interface c/i code macro_17.vsd state ind. cmd. i x i r s/t interface info in out unconditional transition pef 81912/81913 functional description data sheet 108 2001-03-30 c/i codes in reset state in the reset state the c/i code 0000 (tim) is issued. this state is entered either after a hardware reset (rst ) or with the c/i code res. c/i codes in deactivated state if the s-transceiver is in state deactivated and receives i0 , the c/i code 0000 (tim) is issued until expiration of the 8 ms timer. otherwise, the c/i code 1111 (di) is issued. 2.5.5.1 c/i codes the table below presents all defined c/i0 codes. a command needs to be applied continuously until the desired action has been initiated. indications are strictly state orientated. refer to the state diagrams in the following sections for commands and indications applicable in various states. ? code lt-s nt cmd ind cmd ind 0 0 0 0 dr tim dr tim 0001res C res C 0010tm1 C tm1 C 0011tm2 C tm2 C 0100C rsy rsy rsy 0101CCCC 0110CCCC 0111CCCC 1 0 0 0 ar ar ar ar 1001CCCC 1010arl C arl C 1011C cvr C cvr 1100C ai ai ai 1101CCCC 1110C C ail C 1 1 1 1 dc di dc di pef 81912/81913 functional description data sheet 109 2001-03-30 receive infos on s/t i0 info 0 detected i0 level detected (signal different to i0) i3 info 3 detected i3 any info other than info 3 transmit infos on s/t i0 info 0 i2 info 2 i4 info 4 it send single pulses (tm1). send continuous pulses (tm2). pef 81912/81913 functional description data sheet 110 2001-03-30 2.5.5.2 state machine nt mode ? figure 54 state machine nt mode note: state test mode can be entered from any state except from state test mode itself, i.e. c/i-code tmi must not be followed by c/i-code tmj directly. g2 pend. act ar ard i2 i3 reset tim res i0 * g1 i0 detected ar dc i0 * g2 lost framing s/t rsy aid ard i2 i3 g1 deactivated di tim dc i0 i0 statem_nt_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 i3*aid 2) rst ard 1) g2 wait for aid ai ard i2 i3 g3 lost framing u rsy rsy i2 * g3 activated ai aid i4 i3 ard 1) aid 2) i3*ard 1) i3*ard dr dr dr rsy rsy dr rsy ard 1) aid 2) 1) : ard = ar or arl 2) :aid=aiorail ard 1) i3*aid 2) (i0*8ms) pef 81912/81913 functional description data sheet 111 2001-03-30 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom ? -2 interface. g1 i0 detected an info 0 is detected on the s/t-interface, translated to an activation request indication in the c/i channel. the s-transceiver is waiting for an ar command, which normally indicates that the transmission line upstream is synchronized. g2 pending activation as a result of the ard command, an info 2 is sent on the s/t-interface. info 3 is not yet received. in case of arl command, loop 2 is closed. g2 wait for aid info 3 was received, info 2 continues to be transmitted while the s-transceiver waits for a switch-through command aid from the device upstream. g3 activated info 4 is sent on the s/t-interface as a result of the switch through command aid: the b and d-channels are transparent. on the command ail, loop 2 is closed. g2 lost framing s/t this state is reached when the transceiver has lost synchronism in the state g3 activated. g3 lost framing u on receiving an rsy command which usually indicates that synchronization has been lost on the transmission line, the s-transceiver transmits info 2. g4 pending deactivation this state is triggered by a deactivation request dr, and is an unstable state. indication di (state g4 wait for dr) is issued by the transceiver when: either info0 is received for a duration of 16 ms or an internal timer of 32 ms expires. pef 81912/81913 functional description data sheet 112 2001-03-30 g4 wait for dr final state after a deactivation request. the s-transceiver remains in this state until dc is issued. unconditional states test mode tm1 send single pulses test mode tm2 send continuous pulses c/i commands ? command abbr. code remark deactivation request dr 0000 deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. activation indication ai 1100 activation indication. synchronous receiver, i.e. activation completed. pef 81912/81913 functional description data sheet 113 2001-03-30 activation indication loop ail 1110 activation indication loop deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during deactivation procedure. receiver not synchronous rsy 0100 receiver is not synchronous. activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request. command abbr. code remark pef 81912/81913 functional description data sheet 114 2001-03-30 2.5.5.3 state machine lt-s mode ? figure 55 state machine lt-s mode note: state test mode can be entered from any state except from state test mode itself, i.e. c/i-code tmi must not be followed by c/i-code tmj directly. g3 activated ai dc ard i4 i3 reset tim res i0 * g2 pend. act. ar dc ard i2 i3 g2 lost framing s/t rsy dc ard i2 i3 g1 deactivated di tim dc i0 i0 1) :ard=arorarl statem_lts_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 dr dr i3 i3 rst (i0*8ms)+ard 1) pef 81912/81913 functional description data sheet 115 2001-03-30 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom ? -2 interface. g2 pending activation as a result of an info 0 detected on the s/t line or an ard command, the s-transceiver begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. g3 activated normal state where info 4 is transmitted to the s/t-interface. the transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter keeps on sending info 4. g2 lost framing this state is reached when the s-transceiver has lost synchronism in the state g3 activated. g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: indication di (state g4 wait for dr.) is issued by the s-transceiver when: either info0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the transceiver remains in this state until dc is issued. unconditional states test mode - tm1 single alternating pulses are sent on the s/t-interface. pef 81912/81913 functional description data sheet 116 2001-03-30 test mode - tm2 continuous alternating pulses are sent on the s/t-interface. ? command abbr. code remark deactivation request dr 0000 dr - deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during activation procedure in g1. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request pef 81912/81913 functional description data sheet 117 2001-03-30 2.5.6 s-transceiver enable / disable the layer-1 part of the s-transceiver can be enabled/disabled with the two bits s_conf0.dis_tr and s_conf2.dis_tx. if dis_tx=1 the transmit buffers are disabled. the receiver will monitor for incoming data in this configuration. by default the transmitter is disabled (dis_tx = 1). if the transceiver is disabled (dis_tr = 1, dis_tx = dont care) all layer-1 functions are disabled including the level detection circuit of the receiver. in this case the power consumption of the s-transceiver is reduced to a minimum. pef 81912/81913 functional description data sheet 118 2001-03-30 2.5.7 interrupt structure s-transceiver ? figure 56 interrupt structure s-transceiver 0 0 0 0 ld ric sqc sqw 1 1 1 1 ld ric sqc sqw istas masks 0 7 reserved interr.vsd s ista mask int level detect sqx3 0 mfen 0 0 sqx1 sqx2 sqx4 msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 rinf 0 fecv 0 fsyn 0 ld s_sta sqrr sqxr 0 7 0 7 0 7 0 7 pef 81912/81913 functional description data sheet 119 2001-03-30 2.6 hdlc controller the q-smint ? ix contains a hdlc controller which can be used for the layer-2 functions of the d- channel protocol (lapd) or b-channel protocols. by setting the enable hdlc channel bits (en_d, en_b1h, en_b2h) in the hci_cr register the hdlc controller can access the d or b-channels or any combination of them e.g. 18 bit idsl data (2b+d). the hdlc transceiver in the q-smint ? ix performs the framing functions used in hdlc based communication: flag generation/recognition, bit stuffing, crc check and address recognition. the hdlc controller contains a 64 byte fifo in both receive and transmit direction which is implemented as a cyclic buffer. the transceivers read and write data sequentially with constant data rate, whereas the data transfer between fifo and m c interface uses a block oriented protocol with variable block sizes. 2.6.1 message transfer modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be programmed in a flexible way to satisfy different system requirements. the structure of a lapd two-byte address is shown below. ? for the address recognition the q-smint ? ix contains four programmable registers for individual sapi and tei values (sap1, 2 and tei1, 2), plus two fixed values for the group sapi (sapg = fe or fc) and tei (teig = ff). the received c/r bit is excluded from the address comparison. ea is the address field extension bit which is set to 1 according to the lapd protocol. there are 5 different operating modes which can be selected via the mode selection bits mds2-0 in the modeh register: non-auto mode (mds2-0 = 01x) characteristics: full address recognition with one-byte (mds = 010) or two-byte (mds = 011) address comparison all frames with valid addresses are accepted and the bytes following the address are transferred to the m p via rfifo. additional information is available in rsta. high address byte low address byte sapi1, 2, sapg c/r 0 tei 1, 2, teig ea pef 81912/81913 functional description data sheet 120 2001-03-30 transparent mode 0 (mds2-0 = 110). characteristics: no address recognition every received frame is stored in rfifo (first byte after opening flag to crc field). additional information can be read from rsta. transparent mode 1 (mds2-0 = 111). characteristics: sapi recognition a comparison is performed on the first byte after the opening flag with sap1, sap2 and group sapi (fe h /fc h ). in the case of a match, all the following bytes are stored in rfifo. additional information can be read from rsta. transparent mode 2 (mds2-0 = 101). characteristics: tei recognition a comparison is performed only on the second byte after the opening flag, with tei1, tei2 and group tei (ff h ). in case of a match the rest of the frame is stored in the rfifo. additional information is available in rsta. extended transparent mode (mds2-0 = 100). characteristics: fully transparent in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/ check and bitstuffing mechanism. this allows user specific protocol variations. also refer to chapter 2.6.5 . 2.6.2 data reception 2.6.2.1 structure and control of the receive fifo the 64-byte cyclic rfifo buffer has variable fifo block sizes (thresholds) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding rfbs bits in the exmr register. the variable block size allows an optimized hdlc processing concerning frame length, i/o throughput and interrupt load. the transfer protocol between hdlc fifo and microcontroller is block orientated with the microcontroller as master. the control of the data transfer between the cpu and the q-smint ? ix is handled via interrupts (q-smint ? ix ? host) and commands (host ? q-smint ? ix). there are three different interrupt indications in the istah register concerned with the reception of data: C rpf ( r eceive p ool f ull) interrupt, indicating that a data block of the selected length (exmr.rfbs) can be read from rfifo. the message which is currently received exceeds the block size so further blocks will be received to complete the message. pef 81912/81913 functional description data sheet 121 2001-03-30 C rme ( r eceive m essage e nd) interrupt, indicating that the reception of one message has been completed and the message has been stored in the rfifo. either C a short message has been received (message length the defined block size (exmr.rfbs) or C the last part of a long message has been received (message length > the defined block size (exmr.rfbs)). C rfo ( r eceive f rame o verflow) interrupt, indicating that a complete frame could not be stored in rfifo and is therefore lost as the rfifo is occupied. this occurs if the host fails to respond quick enough to rpf/rme interrupts since previous data was not read by the host. there are two control commands that are used with the reception of data: C rmc ( r eceive m essage c omplete) command, telling the q-smint ? ix that a data block has been read from the rfifo and the corresponding fifo space can be released for new receive data. C rres ( r eceiver r eset) command, resetting the hdlc receiver and clearing the receive fifo of any data (e.g. used before start of reception). it has to be used after a change of the message transfer mode. rres does not clear pending interrupt indications of the receiver, but have to be be cleared by reading these interrupts. note: the significant interrupts and commands are underlined as only these are usually used during a normal reception sequence. the following description of the receive fifio operation is illustrated in figure 57 for a rfifo block size (threshold) of 16 and 32 bytes. the rfifo requests service from the microcontroller by setting a bit in the istah register, which causes an interrupt (rpf, rme, rfo). the microcontroller then reads status information (rbch,rbcl), data from the rfifo and changes the rfifo block size (exmr.rfbs). a block transfer is completed by the microcontroller via a receive message complete (cmdr.rmc) command. this causes the space of the transferred bytes being released for new data and in case the frame was complete (rme) the reset of the receive byte counter rbc (rbch,rbcl). 1) the total length of the frame is contained in the rbch and rbcl registers which contain a 12 bit number (rbc11...0), so frames up to 4095 byte length can be counted. if a frame is longer than 4095 bytes, the rbch.ov (overflow) bit will be set. the least significant bits of rbcl contain the number of valid bytes in the last data block indicated by rme (length of last data block selected block size). table 32 shows which rbc bits contain the number of bytes in the last data block or number of complete data blocks, 1) if rmc is omitted, then no new interrupt can be generated. pef 81912/81913 functional description data sheet 122 2001-03-30 respectively. if the number of bytes in the last data block is 0 the length of the last received block is equal to the block size. ? the transfer block size (exmr.rfbs) is 32 bytes by default. if it is necessary to react to an incoming frame within the first few bytes the microcontroller can set the rfifo block size to a smaller value. each time a cmdr.rmc or cmdr.rres command is issued, the rfifo access controller sets its block size to the value specified in exmr.rfbs, so the microcontroller has to write the new value for rfbs before the rmc command. when setting an initial value for rfbs before the first hdlc activities, a rres command must be issued afterwards. the rfifo can hold any number of frames fitting in the 64 bytes independent on rfbs. at the end of a frame, the rsta byte is always inserted. all generated interrupts are inserted together with all additional information into a wait line to be individually passed to the host. for example if several data blocks have been received to be read by the host and the host acknowledges the current block, a new rpf or rme interrupt from the wait line is immediately generated to indicate new data. table 32 receive byte count with rbc11...0 in the rbch and rbcl registers exmr.rfbs bits selected block size number of complete data blocks in bytes in the last data block in 00 32 byte rbc11...5 rbc4...0 01 16 byte rbc11...4 rbc3...0 10 8 byte rbc11...3 rbc2...0 11 4 byte rbc11...2 rbc1...0 pef 81912/81913 functional description data sheet 123 2001-03-30 ? figure 57 rfifo operation hdlc receiver 32 16 8 4 rpf rfifo p rbc=4h ram hdlc receiver rfifo access controller 32 16 8 4 rfbs=01 ram exmr.rfbs=01 rmc exmr.rfbs=11 so after the first 4 bytes of a new frame have been stored in the fifo a receive pool full interrupt istah.rpf the p has read the 4 bytes, sets rfbs=01 (16 bytes) and completes the block transfer by a cmdr.rmc command. following cmdr.rmc the 4 bytes of the last block are deleted. rfacc rfacc is set. rfifo access controller rfbs=11 hdlc receiver 32 16 8 rpf rfifo p rbc=14h ram rsta rsta rsta the hdlc receiver has written further data into the fifo. when a frame is complete, a status byte (rsta) is appended. fifo. when the rfacc detects 16 valid bytes, it sets a rpf interrupt. the p reads the 16 bytes hdlc receiver 32 16 8 rme rfifo rbc=16h ram rsta rsta rsta after the rmc acknowledgement the the frame, therefore it asserts a rme interupt and increments the rbc counter by 2. rmc rfacc rfacc meanwhile two more short frames have been received. and acknowledges the transfer by setting cmdr.rmc. this causes the space occupied by the 16 bytes being released. p rfifo access controller rfbs=01 rfifo access controller rfbs=01 rfacc detects a rsta byte, i.e. end of pef 81912/81913 functional description data sheet 124 2001-03-30 possible error conditions during reception of frames if parts of a frame get lost because the receive fifo is full, the receive data overflow (rdo) byte in the rsta byte will be set. if a complete frame is lost, i.e. if the fifo is full when a new frame is received, the receiver will assert a receive frame overflow (rfo) interrupt. the microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it reads the same data again and again. on the other hand, if it does not read or does not want to read all data, they are deleted anyway after the rmc command. if the microcontroller tries to read data without a prior rme or rpf interrupt, the content of the rfifo would not be corrupted, but new data is only transferred to the host as long as new valid data is available in the rfifo, otherwise the last data is read again and again. the general procedures for a data reception sequence are outlined in the flow diagram in figure 58 . pef 81912/81913 functional description data sheet 125 2001-03-30 ? figure 58 data reception procedures figure 59 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. the fifo threshold (block size) is set to 32 bytes (exmr.rfbs = 00) in this example: ? after 32 bytes have been received off frame 1 a rpf interrupt is generated to indicate that a data block can be read from the rfifo. hdlc_rflow.vsd start receive message end rme ? receive pool full rpf ? read counter rd_count := rfbs or rd_count := rbc read rd_count bytes from rfifo receive message complete write rmc change block size write exmr.rfbs (optional) read rbc rd_count := rbc y y n n * 1) rbc = rbch + rbcl register rfbs: refer to exmr register in case of rme the last byte in rfifo contains the receive status information rsta * 1) pef 81912/81913 functional description data sheet 126 2001-03-30 ? the host reads the first data block from rfifo and acknowledges the reception by rmc. meanwhile the second data block is received and stored in rfifo. ? the second 32 byte block is indicated by rpf which is read and acknowledged by the host as described before. ? the reception of the remaining 4 bytes are indicated by rme (i.e. the receive status in rsta register is always appended to the end of a frame). ? the host gets the number of received bytes (count = 5) from rbcl/rbch and reads out the rfifo and optionally the status register rsta. the frame is acknowledged by rmc. ? the second frame is received and indicated by rme interrupt. ? the host gets the number of bytes (count = 13) from rbcl/rbch and reads out the rfifo and status registers. the rfifo is acknowledged by rmc. ? the third frame is transferred in the same way. ? figure 59 reception sequence example 2.6.2.2 receive frame structure the management of the received hdlc frames as affected by the different operating modes (see chapter 2.6.1 ) is shown in figure 60 . fifoseq_rec.vsd * 1) the last byte contains the receive status information pef 81912/81913 functional description data sheet 127 2001-03-30 ? figure 60 receive data flow note: the figure shows all modes except the extended transparent mode as this mode uses no typical frame structure or address recognition. data is transferred purely transparent. flag macro_12.vsd mds0 mds mds md ctrl crc flag i dd ss d s s addr * s * 0 0 * * 0 0 0 s s s * * * s * s s s * 0 * d !"" # s$%&'( % ) *"+ ," s ) " ," * "''$ ) " "# -m . / * )) "''$ ) " "# -m .s / * s # + ' " ') " # 0" )) * s * * s * * s * * # s ," ) ) + #% ) " . pef 81912/81913 functional description data sheet 128 2001-03-30 the q-smint ? ix indicates to the host that a new data block can be read from the rfifo by means of a rpf interrupt (see previous chapter). user data is stored in the rfifo and information about the received frame is available in the rsta, rbcl and rbch registers which are listed in table 33 . the rsta register is appended as last byte to the end of a frame. 2.6.3 data transmission 2.6.3.1 structure and control of the transmit fifo the 64-byte cyclic xfifo buffer has variable fifo block sizes (thresholds) of 16 or 32 bytes, selectable by the xfbs bit in the exmr register. there are three different interrupt indications in the istah register concerned with the transmission of data: table 33 receive information at rme interrupt information register bit mode type of frame (command/ response) rsta c/r non-auto mode, 2-byte address field transparent mode 1 recognition of sapi rsta sa1, 0 non-auto mode, 2-byte address field transparent mode 1 recognition of tei rsta ta all except transparent mode 0 and 1 result of crc check (correct/incorrect) rsta crc all valid frame rsta vfr all abort condition detected (yes/no) rsta rab all data overflow during reception of a frame (yes/no) rsta rdo all number of bytes received in rfifo rbcl rbcx-0 all (see table 32 ) message length rbcl rbch rbc11-0 all rfifo overflow rbch ov all pef 81912/81913 functional description data sheet 129 2001-03-30 C xpr ( t ransmit p ool r eady) interrupt, indicating that a data block of up to 16 or 32 bytes (block size selected via exmr:xfbs) can be written to the xfifo. a xpr interrupt is generated either C after a xres (transmitter reset) command (which is issued for example for frame abort) or C when a data block from the xfifo is transmitted and the corresponding fifo space is released to accept further data from the host. C xdu ( t ransmit d ata u nderrun) interrupt, indicating that the transmission of the current frame has been aborted (seven consecutive 1s are transmitted) as the xfifo holds no further transmit data. this occurs if the host fails to respond to a xpr interrupt quick enough. C xmr ( t ransmit m essage r epeat) interrupt, indicating that the transmission of the complete last frame has to be repeated as a collision on the s bus has been detected while the first data bytes have already been overwritten with new data. so the xfifo does not hold the first data bytes of the frame (the hdlc transmitter is stopped if a collision on the s bus has been detected). the occurrence of a xdu or xmr interrupt clears the xfifo and a xpr interrupt is issued together with a xdu or xmr interrupt, respectively. data cannot be written to the xfifo as long as a xdu/xmr interrupt is pending. three different control commands are used for transmission of data: C xtf ( t ransmit t ransparent f rame) command, telling the q-smint ? ix that up to 16 or 32 bytes (according to selected block size) have been written to the xfifo and should be transmitted. a start flag is generated automatically. C xme ( t ransmit m essage e nd) command, telling the q-smint ? ix that the last data block written to the xfifo completes the corresponding frame and should be transmitted. this implies that according to the selected mode a frame end (crc + closing flag) is generated and appended to the frame. C xres ( t ransmitter r eset) command, resetting the hdlc transmitter and clearing the transmit fifo of any data. after a xres command the transmitter always sends an abort sequence, i.e. this command can be used to abort a transmission. xres does not clear pending interrupt indications of the transmitter, but has to be be cleared by reading these interrupts. optionally two additional status conditions can be read by the host: C xdov ( t ransmit d ata o verflow), indicating that the data block size has been exceeded, i.e. more than 16 or 32 bytes were entered and data was overwritten. C xfw ( t ransmit f ifo w rite enable), indicating that data can be written to the xfifo. this status flag may be polled instead of or in addition to xpr. note: the significant interrupts and commands are underlined as only these are usually used during a normal transmission sequence. pef 81912/81913 functional description data sheet 130 2001-03-30 the xfifo requests service from the microcontroller by setting a bit in the istah register, which causes an interrupt (xpr, xdu, xmr). the microcontroller can then read the status register star (xfw, xdov), write data in the fifo and it may optionally change the transmit fifo block size (exmr.xfbs) if required. the instant of the initiation of a transmit pool ready (xpr) interrupt after different transmit control commands is listed in table 34 . ? when setting xme the transmitter appends the fcs and the endflag at the end of the frame. when xtf & xme have been set, the xfifo is locked until successful transmission of the current frame, so a consecutive xpr interrupt also indicates successful transmission of the frame, whereas after xme the xpr interrupt is asserted as soon as there is space for one data block in the xfifo. the transfer block size is 32 bytes by default, but sometimes, if the microcontroller has a high computational load, it is useful to increase the maximum reaction time for a xpr interrupt. the maximum reaction time is: t max = (xfifo size - xfbs) / data transmission rate with a selected block size of 16 bytes indicates a xpr interrupt when there are still 48 bytes (64 bytes - 16 bytes) to be transmitted. with a 32 bytes block size the xpr is initiated when there are still 32 bytes (64 bytes - 32 bytes), i.d. the maximum reaction time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt load. a selected block size of 32 or 16 bytes respectively always indicates the available space in the xfifo. so any number of bytes smaller than the selected xfbs may be stored in the fifo during one write block access cycle. similar to rfbs for the receive fifo, a new setting of xfbs takes effect after the next xtf,xme or xres command. xres resets the xfifo. the xfifo can hold any number of frames fitting in the 64 bytes. table 34 xpr interrupt (availability of the xfifo) after xtf, xme commands cmdr. transmit pool ready (xpr) interrupt initiated... xtf as soon as the selected buffer size in the fifo is available xtf & xme after the successful transmission of the closing flag. the transmitter always sends an abort sequence xme as soon as the selected buffer size in the fifo is available, two consecutive frames share flags (endflag = startflag of next frame). pef 81912/81913 functional description data sheet 131 2001-03-30 possible error conditions during transmission of frames if the transmitter sees an empty fifo, i.e. if the microcontroller does not react quickly enough to a xpr interrupt, a xdu (transmit data underrun) interrupt will be raised. if the hdlc channel becomes unavailable during transmission the transmitter tries to repeat the current frame as specified in the lapd protocol. this is impossible after the first data block has been sent (16 or 32 bytes), in this case a xmr transmit message repeat interrupt is set and the microcontroller has to send the whole frame again. if the host fails to respond to a transmit pool ready (xpr) interrupt quickly enough, then transmission of the current frame is aborted, a transmit data underrun (xdu) interrupt is generated and an abort sequence (seven consecutive 1) shall be transmitted. if the c requests transmission of a new frame during a certain time window after the xdu interrupt, then the abort sequence may be overwritten by the start flag of this new frame. however, the abort sequence is transmitted correctly by waiting 8 iom-2 frames before the c requests transmission of a new frame: ? read from address 20 h (register istah): 14 h (xpr and xdu interrupt active) ? wait for 1 ms (e.g. by use of the internal timer of the q-smintix) ? write new frame to xfifo both xmr and xdu interrupts cause a reset of the xfifo. the xfifo is locked while a xmr or xdu interrupt is pending, i.e. all write actions of the microcontroller will be ignored as long as the microcontroller has not read the istah register with the set xdu, xmr interrupts. if the microcontroller writes more data than allowed (16 or 32 bytes) , then the data in the xfifo will be corrupted and the star.xdov bit is set. if this happens, the microcontroller has to abort the transmission by cmdr.xres and start new. the general procedures for a data transmission sequence are outlined in the flow diagram in figure 61 . pef 81912/81913 functional description data sheet 132 2001-03-30 ? figure 61 data transmission procedure the following description gives an example for the transmission of a 76 byte frame with a selected block size of 32 byte (exmr:xfbs=0): ? the host writes 32 bytes to the xfifo, issues a xtf command and waits for a xpr interrupt in order to continue with entering data. ? the q-smint ? ix immediately issues a xpr interrupt (as remaining xfifo space is not used) and starts transmission. ? due to the xpr interrupt the host writes the next 32 bytes to the xfifo, followed by the xtf command, and waits for xpr. macro_13.vsd start transmit pool ready xpr ? issue command -xmeor - xtf+xme write data (upto32bytes) to xfifo n y y n end of message ? end command xtf pef 81912/81913 functional description data sheet 133 2001-03-30 ? as soon as the last byte of the first block is transmitted, the q-smint ? ix issues a xpr interrupt (xfifo space of first data block is free again) and continues transmitting the second block. ? the host writes the remaining 12 bytes of the frame to the xfifo and issues the xtf command together with xme to indicate that this is the end of frame. ? after the last byte of the frame has been transmitted the q-smint ? ix releases a xpr interrupt and the host may proceed with transmission of a new frame. figure 62 transmission sequence example 2.6.3.2 transmit frame structure the transmission of transparent frames (xtf command) is shown in figure 63 . for transparent frames, the whole frame including address and control field must be written to the xfifo. the host configures whether the crc is generated and appended to the frame (default) or not (selected in exmr.xcrc). further, the host selects the interframe time fill signal which is transmitted between hdlc frames (exmr:itf). one option is to send continuous flags (01111110), or an idle sequence (continuous 1s are transmitted), which is used if d-channel access handling (collision resolution on the s bus) is required for example. reprogramming of itf takes effect only after the transmission of the current frame has been completed or after a xres command. transmit frame 76 bytes fifoseq_tran.vsd iom interface cpu interface wr 32 bytes xtf 32 12 32 xpr xpr wr 32 bytes xtf wr 12 bytes xtf+xme xpr pef 81912/81913 functional description data sheet 134 2001-03-30 figure 63 transmit data flow 2.6.4 access to iom ? -2 channels by setting the enable hdlc data bits (en_d, en_b1h, en_b2h) in the hci_cr register the hdlc controller can access the d, b1, b2 channels or any combination of them (e.g. 18 bit idsl data (2b+d). in all modes (except extended transparent mode) sending works always frame aligned, i.e. it starts with the first selected channel whereas reception looks for a flag anywhere in the serial data stream. 2.6.5 extended transparent mode this non-hdlc mode is selected by setting modeh.mds2-0 to 100. in extended transparent mode fully transparent data transmission/reception without hdlc framing is performed i.e. without flag generation/recognition, crc generation/check, bitstuffing mechanism. this allows user specific protocol variations. transmitter the transmitter sends the data out of the fifo without manipulation. transmission is always iom ? -2-frame aligned and byte aligned, i.e. transmission starts in the first selected channel (b1, b2, d, according to the setting of register hci_cr in the iom ? -2 handler) of the next iom ? -2 frame. the fifo indications and commands are the same as in other modes. if the microcontroller sets xtf & xme the transmitter responds with a xpr interrupt after sending the last byte, then it returns to its idle state (sending continuous 1). flag fifoflow_tran.vsd transmit transparent frame tf ctrl crc flag i t t addr * f f * t e is enerate ! e"a#$t% " % is set n& is appen e pef 81912/81913 functional description data sheet 135 2001-03-30 if the collision detection is enabled (modeh.dim = 0x1) the stop go bit (s/g) can be used as a clear-to-send indication as in any other mode. if the s/g bit is set to 1 (stop) during transmission the transmitter responds always with a xmr (transmit message repeat) interrupt and stops transmission. if the microcontroller fails to respond to a xpr interrupt in time and the transmitter runs out of data then it will assert a xdu (transmit data underrun) interrupt. receiver the reception is iom ? -2-frame aligned and byte aligned, like transmission, i.e. reception starts in the first selected channel (b1, b2, d, according to the setting of register hci_cr in the iom ? -2 handler) of the next iom ? -2 frame. the fifo indications and commands are the same as in others modes. all incoming data bytes are stored in the rfifo. if the fifo is full a rfo interrupt is asserted (exmr.sra = 0). note: in the extended transparent mode the exmr register has to be set to xxx00000 2.6.6 timer the timer provides two modes ( table 35 ), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. ? when the programmed period has expired an interrupt is generated (ista.tin). the host controls the timer by setting bit cmdr.sti to start the timer and by writing register timr to stop the timer. after time period t1 an interrupt is generated continuously if cnt=7 or a single interrupt is generated after timer period t if cnt<7 ( figure 64 ). table 35 timer address register modes period 04 h timr periodic 64 ... 2048 ms count down 2.048 ... 14.336 s pef 81912/81913 functional description data sheet 136 2001-03-30 ? figure 64 timer register 2.6.7 hdlc controller interrupts all interrupt sources from the istah register are combined (ored) to a single hdlc controller interrupt signal hint. each of the interrupt sources can individually be masked in the maskh register. a masked interrupt is not indicated in the istah register but remains internally stored and pending until the interrupt is unmasked and read by the host. the individual interrupt sources of the hdlc controller during reception and transmission of data are explained in chapter 2.6.2.1 or chapter 2.6.3.1 respectively. the hdlc controller interrupts xdu and xmr have a special impact on the internal functions. e.g. the transmitter of the hdlc controller is locked if a data underrun condition occurs and the istah.xdu is not read (the interrupt can only be read if unmasked), same applies for xmr. 21150_14 cnt value 76543210 24 h expiration period t1 = (value + 1) x 0.064 sec retry counter 0 ... 6 : count down timer t = cnt x 2.048 sec + t1 7 : periodic timer t = t1 timr1 pef 81912/81913 functional description data sheet 137 2001-03-30 figure 65 interrupt status registers of the hdlc controller 2.6.8 test function the q-smint ? ix provides test and diagnostic functions for the hdlc controller: digital loop via tlp (test loop, tmh register) command bit ( figure 66 ): the tx path of the hdlc controller is still connected to iom ? -2 but it is internally connected with the rx path. all incoming data from the iom ? -2 is ignored. this is used for testing hdlc functionality excluding layer 1 (u-transceiver (loopback between xfifo and rfifo). ? figure 66 layer 2 test loops rme rpf rfo xpr xmr xdu cic st mos s rme rpf rfo xpr xmr xdu maskh istah wov int ista mask cic st mos s wov u u hdlc hdlc tin tin hdlc tmh:tlp = 0 hdlc tmh:tlp = 1 macro_8 iom-2 d ata o u t dat a in iom-2 d ata o u t dat a in pef 81912/81913 functional description data sheet 138 2001-03-30 2.6.9 reset behavior after reset all pointers to the fifos are set to 0, the xpr interrupt is set to 1 but cannot be read by the host as it is masked, i.e. it must be unmasked so it can be read. pef 81912/81913 operational description data sheet 139 2001-03-30 3 operational description 3.1 layer 1 activation/deactivation 3.1.1 complete activation initiated by exchange figure 67 depicts the procedure if activation has been initiated by the exchange side (lt). ? figure 67 complete activation initiated by exchange iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc dc info 0 s 0 c dc u k0 sl0 dc di info 0 di di itd08687.vsd sn0 di tn sn1 sn0 sl1 sl2 (act = 0, dea = 1, uoa = 1) sn2 sn3 (act = 0, sai = 0) uai sl3t (act = 0, dea = 1, uoa = 1) ai info 4 ar tl pu dc 1) ar arm ar ar info 2 ar info 3 ai ar ar 2) sn3 (act = 0, sai = 1) sn3 (act = 1, sai = 1) sl3t (act = 1, dea = 1, uoa = 1) ai ai ai ar8/10 ai sn3t 1) c/i-code dc is not issued in case of simplified state machine is selected sl0 2) c/i-code ar is optional sbcx-x or ipac-x dfe-q q-smintix pef 81912/81913 operational description data sheet 140 2001-03-30 3.1.2 complete activation initiated by te figure 68 depicts the procedure if activation has been initiated by the terminal side (te). ? figure 68 complete activation initiated by te iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc dc info 0 c dc sl0 dc di info 0 di di sn0 di tim pu ar info 1 tim tim pu ar ar ar ar info 2 rsy info 0 info 3 ar ai ai arm uai ai ai ai info 4 ai tn sn1 sn0 sl1 sl2 (act = 0, dea = 1, uoa = 0) sn2 sn3 (act = 0, sai = 1) sl3t (uoa = 1) sn3 (act = 1, sai = 1) sl3t (act = 1, dea = 1, uoa = 1) sn3t itd08688.vsd 1) c/i-code dc is not issued in case of simplified state machine is selected dc 1) sbcx-x or ipac-x dfe-q 8ms ar s 0 u k0 q-smintix pef 81912/81913 operational description data sheet 141 2001-03-30 3.1.3 complete activation initiated by nt figure 69 depicts the procedure if activation has been initiated by the q-smint ? ix itself (e.g. after hook-off of a local analog phone). ? figure 69 complete activation initiated by q-smint ? ix iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 dc dc info 0 c dc sl0 dc di info 0 di tim di itd08689.vsd sn0 arm di pu ar tn sn1 sn0 sl1 sl2 (act = 0, dea = 1, uoa = 0) sn2 sn3 (act = 0, sai = 1) uai sl3t (uoa = 1) ar ar ar info 2 ar info 3 ai ai sn3 (act = 1, sai = 1) ai sl3t (act = 1, dea = 1, uoa = 1) sn3t ai ai info 4 ai dc 1) 1) c/i-code dc is not issued in case of simplified state machine is selected ar sbcx-x or ipac-x dfe-q s 0 u k0 q-smintix pef 81912/81913 operational description data sheet 142 2001-03-30 3.1.4 complete deactivation figure 70 depicts the procedure if deactivation has been initiated. deactivation of layer 1 is always initiated by the exchange. ? figure 70 complete deactivation initiated by exchange iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 ai ai info 4 s 0 c ai sl3t (act = 1, dea = 1, uoa = 1) ar (ar) info 3 ai ai itd08690.vsd sn3t (act = 1, dea = 1) dr deac sl3t (act = 0, dea = 0) sl0 40 ms dr dr tim info 0 di dc sl0 3ms di dc ai u k0 sbcx-x or ipac-x dfe-q info 0 dr di dc di dc & rsy 1) c/i-code dr is issued in case of simplified state machine is selected dc 1) 2) 2) c/i-code ar might be issued before c/i-code dc in case of m4 validation algorithm tll, crc&tll or on change is selected q-smintix pef 81912/81913 operational description data sheet 143 2001-03-30 3.1.5 loop 2 figure 71 depicts the procedure if loop 2 is closed and opened. ? figure 71 loop 2 iom ? -2 te s/t-reference point nt u-reference point lt iom ? -2 ai info 4 ai sl3t (act = 1, dea = 1, uoa = 1) ar8/10 info 3 ai itd10034.vsd sn3t (act = 1, dea = 1) ar ai c ail ail istau.eoc=1 ai ai 2b+d 2b+d 2b+d eoc: lbbd: act = 1 mon0:lbbd ai ai eoc:rtn:act=1 mon0:rtn istau.eoc=1 s 0 u k0 dfe-q sbcx-x or ipac-x q-smintix pef 81912/81913 operational description data sheet 144 2001-03-30 3.2 layer 1 loopbacks test loopbacks are specified by the national ptts in order to facilitate the location of defect systems. four different loopbacks are defined. the position of each loopback is illustrated in figure 72 . ? figure 72 test loopbacks loopbacks #1, #1a and #2 are controlled by the exchange. loopback #3 is controlled locally on the remote side. all four loopback types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. only the data looped back internally is processed; signals on the receive pins are ignored. the propagation delay of actually looped b and d channels data must be identical in all loopbacks. besides the remote controlled loopback stimulation via the eoc channel, the q- smint ? ix features also direct loopback control via its register set. 3.2.1 analog loopback u-transceiver (no. 3) loopback #3 is closed by the u-transceiver as near to the u-interface as possible, i.e. the loop is closed in the analog part by short circuiting the output to the input. the signal on the line is ignored in this state. for this reason it is also called analog loopback. all analog signals will still be passed on to the u-interface. before an analog loopback is closed by the appropriate c/i-command arl (activation request loopback 3), the u-transceiver shall have been reset. iom ? -2 pbx or te u-transceiver iom ? -2 iom ? -2 iom ? -2 u-transceiver u-transceiver u-transceiver u-transceiver u-transceiver loop 2 loop 3 loop 2 loop 1 a loop 2 loop 1 s-bus nt u u loop 2 repeater (optional) s-transceiver layer-1 controller layer-1 controller iom-2 exchange loop_2b1q.emf pef 81912/81913 operational description data sheet 145 2001-03-30 in order to open an analog loopback correctly, force the u-transceiver into the reset state. this ensures that the echo coefficients and equalizer coefficients will converge correctly when activating anew. 3.2.2 analog loop-back s-transceiver the q-smint ? ix provides test and diagnostic functions for the s/t interface: the internal local loop (internal loop a) is activated by a c/i command arl or by setting the bit lp_a (loop analog) in the s_cmd register if the layer-1 statemachine is disabled. the transmit data of the transmitter is looped back internally to the receiver. the data of the iom ? -2 input b- and d-channels are looped back to the output b- and d-channels. the s/t interface level detector is enabled, i.e. if a level is detected this will be reported by the resynchronization indication (rsy) but the loop function is not affected. depending on the dis_tx bit in the s_conf2 register the internal local loop can be transparent or non transparent to the s/t line. the external local loop (external loop a) is activated in the same way as the internal local loop described above. additionally the exlp bit in the s_conf0 register has to be programmed and the loop has to be closed externally as described in figure 73 . the s/t interface level detector is disabled. ? figure 73 external loop at the s/t-interface scout-s(x) sx1 sx2 sr1 sr2 100 w 100 w pef 81912/81913 operational description data sheet 146 2001-03-30 3.2.3 loopback no.2 for loopback #2 several alternatives exist. both the type of loopback and the location may vary. the following loopback types belong to the loopback-#2 category: ? complete loopback (b1,b2,d), in the u-transceiver ? complete loopback (b1,b2,d), in a downstream device ? b1-channel loopback, always performed in the u-transceiver ? b2-channel loopback, always performed in the u-transceiver all loop variations performed by the u-transceiver are closed as near to the internal iom ? -2 interface as possible. normally loopback #2 is controlled by the exchange. the maintenance channel is used for this purpose. all loopback functions are latched. this allows channel b1 and channel b2 to be looped back simultaneously. 3.2.3.1 complete loopback when receiving the request for a complete loopback, the u transceiver passes it on to the downstream device, e.g. the s-bus transceiver. this is achieved by issuing the c/i- code ail in the transparent state or c/i = arl in states different than transparent (note: this holds true only for the eoc automode). the u transceiver may be commanded to close the complete loopback itself. figure 74 illustrates the two options. ? figure 74 complete loopback options in nt-mode the complete loopback is either opened under control of the exchange via the maintenance channel or locally controlled via the c. no reset is required for loopback #2. the line stays active and is ready for data transmission. 2b+d 2b+d loop request u loop command l p2bymon8.vsd u-transceiver controller s-transceiver loop command pef 81912/81913 operational description data sheet 147 2001-03-30 3.2.3.2 loopback no.2 - single channel loopbacks single channel loopbacks are always performed directly in the u-transceiver. no difference between the b1-channel and the b2-channel loopback control procedure exists. 3.2.4 local loopbacks featured by the loop register besides the standardized remote loopbacks the u-transceiver features additional local loopbacks for enhanced test and debugging facilities. the local loopbacks that are featured by register loop are shown in figure 75 . they are closed in the u-transceiver itself and can be activated regardless of the current operational status. by the loop register it can be configured whether the loopback is closed only for the b1 and/or b2 or for 2b+d channels and whether the loopback is closed towards the internal iom ? -2 interface or towards the u-interface. by default the loopbacks are set to transparent mode. in transparent mode the data is both passed on and looped back. in non-transparent mode the data is not forwarded but substituted by 1s (idle code). besides the loopbacks in the system interface an additional digital loopback (dlb), the framer/ deframer loopback, is featured. it allows to test most digital functions of the u- transceiver besides the signal processing blocks. pef 81912/81913 operational description data sheet 148 2001-03-30 ? figure 75 loopbacks featured by register loop iom-2 interface echo canceller + activation/ deactivation controller timing recovery digital part loopreg.emf loop.dlb= 1 a g c equalizer pdm filter bandgap, bias, refer. analog part line interface unit dac sd sd sd sd adc tx-fifo rx-fifo loop.lb1=1 loop.lb2=1 loop.lbbd= 1 & loop.u/iom= 1 loop.lb1=1 loop.lb2=1 loop.lbbd= 1 & loop.u/iom= 0 iom-2 interface echo canceller + timing recovery bandgap, bias, refer. analog part line interface unit tx-fifo rx-fifo a g c equalizer pdm filter sd sd sd sd adc dac digital part u-transceiver u-de- framing de- scrambler scrambler 2b1q u- framing activation/ deactivation controller u-transceiver scrambler u- framing u-de- framing de- scrambler 2b1q 2b1q 2b1q pef 81912/81913 operational description data sheet 149 2001-03-30 3.3 external circuitry 3.3.1 power supply blocking recommendation the following blocking circuitry is suggested. ? figure 76 power supply blocking 3.3.2 u-transceiver the q-smint ? ix is connected to the twisted pair via a transformer. figure 77 shows the recommended external circuitry. the recommended protection circuitry is not displayed. note: the integrated hybrid as specified for version 1.1 is no more available in version 1.3 and an external hybrid is required. vddd vddd vssd vssd vdda_sr vdda_ur vdda_ux vdda_sx vssa_ur vssa_ux vssa_sr vssa_sx 100nf 100nf 100nf 100nf 100nf 100nf gnd 3.3v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) blocking_caps_smint.vsd pef 81912/81913 operational description data sheet 150 2001-03-30 ?. figure 77 external circuitry u-transceiver u-transformer parameters the following table 36 lists parameters of typical u-transformers: table 36 u-transformer parameters u-transformer parameters symbol value unit u-transformer ratio; device side : line side n1 : 2 main inductance of windings on the line side l h 14.5 mh leakage inductance of windings on the line side l s <75 h coupling capacitance between the windings on the device side and the windings on the line side c k 100 pf dc resistance of the windings on device side r b 2.5 1) w dc resistance of the windings on line side r l 5 1) 1) r b / r l according to equation[2] w loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 81912/81913 operational description data sheet 151 2001-03-30 resistors of the external hybrid r3, r4 and r t r3 = 1.3 k w r4 = 1.0 k w r t = 9.5 w resistors on the line side r ptc / chip side r t optional use of up to 2x20 w resistors (2xr ptc ) on the line side of the transformer requires compensation resistors r comp depending on r ptc : 2r ptc + 8r comp = 40 w (1) 2r ptc + 4(2r comp + 2r t + r out + r b ) + r l = 135 w (2) r b , r l : see table 36 r out : see table 43 27 nf capacitor c to achieve optimum performance the 27 nf capacitor should be mkt. a ceramic capacitor is not recommended. tolerances ? rs: 1% ? c=27 nf: 10-20% ? l=14.5 mh: 10% 3.3.3 s-transceiver in order to comply to the physical requirements of itu recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the s-transceiver needs some additional circuitry. s-transformer parameters the following table 37 lists parameters of a typical s-transformer: pef 81912/81913 operational description data sheet 152 2001-03-30 table 37 s-transformer parameters transmitter the transmitter requires external resistors r stx = 47 w in order to adjust the output voltage to the pulse mask (nominal 750 mv according to itu i.430, to be tested with the test mode tm1) on the one hand and in order to meet the output impedance of minimum 20 w on the other hand (to be tested with the testmode continuous pulses) on the other hand. note: the resistance of the s-transformer must be taken into account when dimensioning the external resistors r stx . if the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. ? figure 78 external circuitry s-interface transmitter transformer parameters symbol value unit transformer ratio; device side : line side n2 : 1 main inductance of windings on the line side l h typ. 30 mh leakage inductance of windings on the line side l s typ. <3 h coupling capacitance between the windings on the device side and the windings on the line side c k typ. <100 pf dc resistance of the windings on device side r b typ. 2.4 w dc resistance of the windings on line side r l typ. 1.4 w 20...40 47 sx1 sx2 2:1 gnd v dd 47 dc point extcirc_s.vsd pef 81912/81913 operational description data sheet 153 2001-03-30 receiver the receiver of the s-transceiver is symmetrical. 10 k w overall resistance are recommended in each receive path. it is preferable to split the resistance into two resistors for each line. this allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 khz input impedance test of itu i.430 [8] and ets 300012-1). the remaining resistance (1.8 k w ) protects the s- transceiver itself from input current peaks. ? figure 79 external circuitry s-interface receiver 3.3.4 oscillator circuitry figure 80 illustrates the recommended oscillator circuit. ? figure 80 crystal oscillator 1k8 1k8 sr1 sr2 2:1 gnd v dd 8k2 8k2 dc point extcirc_s.vsd 15.36 mhz xout xin c ld c ld pef 81912/81913 operational description data sheet 154 2001-03-30 table 38 crystal parameters external components and parasitics the load capacitance c l is computed from the external capacitances c ld , the parasitic capacitances c par (pin and pcb capacitances to ground and v dd ) and the stray capacitance c io between xin and xout: for a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances c ld , which is usually the only variable to be determined by the circuit designer. typical values for the capacitances c ld connected to the crystal are 22 - 33 pf. 3.3.5 general ? low power leds ? mlt input supports C apc13112 C at&t lh1465ab C discrete as proposed by infineon parameter symbol limit values unit frequency f 15.36 mhz frequency calibration tolerance +/-60 ppm load capacitance c l 20 pf max. resonance resistance r1 20 w max. shunt capacitance c 0 7pf oscillator mode fundamental c l c ld c par + () c ld c par + () c ld c par + () c ld c par + () + ------------------------------------------------------------------------ c io + = pef 81912/81913 register description data sheet 155 2001-03-30 4 register description 4.1 address space figure 81 address space iom ? -2 handler interrupt, global registers 40 h 60 h (cda, tsdp, cr, sti) u-transceiver 7d h s-transceiver 3c h monitor handler 5c h hdlc controller, ci reg. hdlc rfifo/xfifo 00 h 20 h 30 h pef 81912/81913 register description data sheet 156 2001-03-30 4.2 interrupts special events in the q-smint ? ix are indicated by means of a single interrupt output, which requests the host to read status information from the q-smint ? ix or transfer data from/to the q-smint ? ix. since only one int request output is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the q-smint ? ix. the structure of the interrupt status registers is shown in figure 82 . figure 82 q-smint ? ix interrupt status registers mlt m4 mlt cic st mos s wov int sti11 ista mask sqc msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 cic1 ci1e cic0 cir0 istas cix1 ric sqc ric masks ld ld cic st mos s wov mre mdr mie mda mer mab mosr mocr sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 sqw sqw ack11 ack10 ack20 ack21 asti uu istau masku ci fe/nebe m56 eoc 6ms 12ms ci fe/nebe m56 m4 eoc 6ms 12ms rme rpf rfo xpr xmr xdu rme rpf rfo xpr xmr xdu maskh istah hdlc hdlc tin tin pef 81912/81913 register description data sheet 157 2001-03-30 after the q-smint ? ix has requested an interrupt by setting its int pin to low, the host must read first the q-smint ? ix interrupt status register (ista) in the associated interrupt service routine. the int pin of the q-smint ? ix remains active until all interrupt sources are cleared. therefore, it is possible that the int pin is still active when the interrupt service routine is finished. each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the mask register. for some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. this can be done by masking all interrupts at the end of the interrupt service routine (writing ff h into the mask register) and writing back the old mask to the mask register. pef 81912/81913 register description data sheet 158 2001-03-30 4.3 register summary r(0) = reserved, implemented as zero. hdlc control registers, ci handler name 7 6 5 4 3 2 1 0 addr r/w res rfifo d-channel receive fifo 00 h - 1f h r xfifo d-channel transmit fifo 00 h - 1f h w istah rme rpf rfo xpr xmr xdu r(0) r(0) 20 h r10 h maskh rme rpf rfo xpr xmr xdu 0 0 20 h wfc h star xdov xfw r(0) r(0) raci r(0) xaci r(0) 21 h r40 h cmdr rmc rres 0 sti xtf 0 xme xres 21 h w00 h modeh mds2 mds1 mds0 r(0) rac dim2 dim1 dim0 22 h r/w c0 h exmr xfbs rfbs sra xcrc rcrc r(0) itf 23 h r/w 00 h timr cnt value 24 h r/w 00 h sap1 sapi1 0 mha 25 h wfc h sap2 sapi2 0 mla 26 h wfc h rbcl rbc7 rbc0 26 h r00 h rbch r(0) r(0) r(0) ov rbc11 rbc8 27 h r00 h tei1 tei1 ea1 27 h wff h tei2 tei2 ea1 28 h wff h rsta vfr rdo crc rab sa1 sa0 c/r ta 28 h r0f h tmh r(0) r(0) r(0) r(0) r(0) r(0) r(0) tlp 29 h r/w 00 h reserved 2a h - 2d h pef 81912/81913 register description data sheet 159 2001-03-30 cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h pef 81912/81913 register description data sheet 160 2001-03-30 s-transceiver name76543210addrr/wres s_ conf0 dis_ tr bus en_ icv 0 l1sw 0 exlp 0 30 h r/w 40 h reserved 31 h s_ conf2 dis_ tx 000000032 h r/w 80 h s_sta rinf 0 icv 0 fsyn 0 ld 33 h r00 h s_cmd xinf dprio 1 pd lp_a 0 34 h r/w 08 h sqrr msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 35 h r00 h sqxr 0 mfen 0 0 sqx1 sqx2 sqx3 sqx4 35 h w00 h reserved 36 h -37 h istas 0 x x x ld ric sqc sqw 38 h r00 h masks 1 1 1 1 ld ric sqc sqw 39 h r/w ff h s_ mode 0000dch_ inh mode2-0 3a h r/w 02 h reserved 3b h pef 81912/81913 register description data sheet 161 2001-03-30 interrupt, general configuration name 7 6 5 4 3 2 1 0 addr r/w res ista u st cic tin wov s mos hdlc 3c h r00 h mask u st cic tin wov s mos hdlc 3c h wff h mode1 mclk cds wtc1 wtc2 cfs rss2 rss1 3d h r/w 04 h mode2 led2 led1 ledc 0 0 0 amod ppsdx 3e h r/w 00 h id 0 0 design 3f h r01 h sres 0 0 res_ ci/tic 0res_ hdlc 0 res_ s res_ u 3f h w00 h pef 81912/81913 register description data sheet 162 2001-03-30 iom handler (timeslot, data port selection, cda data and cda control register) name 76543210addrr/wres cda10 controller data access register 40 h r/w ff h cda11 controller data access register 41 h r/w ff h cda20 controller data access register 42 h r/w ff h cda21 controller data access register 43 h r/w ff h cda_ tsdp10 dps 0 0 0 tss 44 h r/w 00 h cda_ tsdp11 dps 0 0 0 tss 45 h r/w 01 h cda_ tsdp20 dps 0 0 0 tss 46 h r/w 80 h cda_ tsdp21 dps 0 0 0 tss 47 h r/w 81 h reserved 48 h - 4b h s_ tsdp_ b1 dps 0 0 0 tss 4c h r/w 84 h s_ tsdp_ b2 dps 0 0 0 tss 4d h r/w 85 h cda1_ cr 0 0en_ tbm en_i1 en_i0 en_o1 en_o0 swap 4e h r/w 00 h cda2_ cr 0 0en_ tbm en_i1 en_i0 en_o1 en_o0 swap 4f h r/w 00 h pef 81912/81913 register description data sheet 163 2001-03-30 iom handler (control registers, synchronous transfer interrupt control) name 7 6 5 4 3 2 1 0 addr r/w res reserved 50 h s_cr 1 ci_cs en_ d en_ b2r en_ b1r en_ b2x en_ b1x d_cs 51 h r/w ff h hci_cr dps_ ci1 en_ ci1 en_d en_ b2h en_ b1h dps_ h hcs 52 h r/w 04 h mon_ cr dps en_ mon 0 000 mcs 53 h r/w 40 h sds1_ cr ens_ tss ens_ tss+1 ens_ tss+3 0tss54 h r/w 00 h sds2_ cr ens_ tss ens_ tss+1 ens_ tss+3 0tss55 h r/w 00 h iom_cr spu 0 0 tic_ dis en_ bcl 0 dis_ od dis_ iom 56 h r/w 08 h mcda mcda21 mcda20 mcda11 mcda10 57 h rff h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0 0 0 0 ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h reserved 5a h - 5b h pef 81912/81913 register description data sheet 164 2001-03-30 monitor handler name 7 6 5 4 3 2 1 0 addr r/w res mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosr mdr mer mda mab 0 0 0 0 5d h r00 h mocr mre mrc mie mxc 0 0 0 0 5e h r/w 00 h msta 0 0 0 0 0 mac 0 tout 5f h r00 h mconf 0 0 0 0 0 0 0 tout 5f h w00 h pef 81912/81913 register description data sheet 165 2001-03-30 register summary u-transceiver name 76543210addrr/wres opmode 0 uci febe mlt 0ci_ sel 0060 h r*/w 14 h mfilt m56 filter m4 filter eoc filter 61 h r*/w 14 h reserved 62 h eocr 0000a1a2a3d/m63 h r0f h i1 i2 i3 i4 i5 i6 i7 i8 64 h ff h eocw 0000a1a2a3d/m65 h w01 h i1 i2 i3 i4 i5 i6 i7 i8 66 h 00 h m4rmask m4 read mask bits 67 h r*/w 00 h m4wmask m4 write mask bits 68 h r*/w a8 h m4r verified m4 bit data of last received superframe 69 h rbe h m4w m4 bit data to be send with next superframe 6a h r*/w be h m56r 0 ms2 ms1 nebe m61 m52 m51 febe 6b h r1f h m56w 1111m61m52m51febe6c h wff h ucir 0000 c/i code output 6d h r00 h uciw 0000 c/i code input 6e h w01 h test 0000ccrc+-1 tones 040 khz 6f h r*/w 00 h loop 0 dlb trans u/iom 1 lbbd lb2 lb1 70 h r*/w 08 h febe febe counter value 71 h r00 h nebe nebe counter value 72 h r00 h reserved 73 h - 79 h pef 81912/81913 register description data sheet 166 2001-03-30 *) read back function for test use note: registers, which are denoted as reserved, may not be accessed by the c, neither for read nor for write operations. 4.4 reset of u-transceiver functions during deactivation or with c/i-code reset the following u-transceiver registers are reset during deactivation or with software reset: istau mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7a h r00 h masku mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r6x h reserved 7e h - 7f h table 39 reset of u-transceiver functions during deactivation or with c/i- code reset register reset to affected bits eocr 0fff h all bits eocw 0100 h all bits m4r be h all bits m4w be h all bits m56r 1f h all bits are reset besides ms2 and ms1 m56w ff h all bits test only bit ccrc is reset loop only the bits lbbd, lb2 and lb1 are reset pef 81912/81913 register description data sheet 167 2001-03-30 4.5 u-transceiver mode register evaluation timing the point of time when mode settings are detected and executed differs with the mode register type. two different behaviors can be classified: ? evaluation and execution after sw-reset (c/i= res) or upon transition out of state deactivated note: write access to these registers/bits is allowed only, while the state machine is in state reset or deactivated. ? immediate evaluation and execution below the mode registers are listed and grouped according to the different evaluation times as stated above. table 40 u-transceiver mode register evaluation timing register affected bits registers evaluated after sw-reset or upon transition out of state deactivated opmode bit uci, mlt mfilt complete register immediate evaluation and execution opmode bit febe, ci_sel m4rmask complete register m4wmask complete register test complete register loop complete register masku complete register pef 81912/81913 register description data sheet 168 2001-03-30 4.6 detailed hdlc control and c/i registers 4.6.1 rfifo - receive fifo rfifo read address: 00-1f h the rfifo contains up to 32 bytes of received data. after an istah.rpf interrupt, a complete data block is available. the block size can be 4, 8, 16, 32 bytes depending on the exmr.rfbs setting. after an istah.rme interrupt, the number of received bytes can be obtained by reading the rbcl register. a read access to any address within the range 00 h -1f h gives access to the current fifo location selected by an internal pointer which is automatically incremented after each read access. this allows for the use of efficient move string type commands by the microcontroller. 4.6.2 xfifo - transmit fifo xfifo write address: 00-1f h depending on exmr.xfbs up to 16 or 32 bytes of transmit data can be written to the xfifo following an istah.xpr interrupt. a write access to any address within the range 00-1f h gives access to the current fifo location selected by an internal pointer which is automatically incremented after each write access. this allows the use of efficient move string type commands by the microcontroller. 70 receive data 70 transmit data pef 81912/81913 register description data sheet 169 2001-03-30 4.6.3 istah - interrupt status register hdlc istah read address: 20 h value after reset: 10 h note: the reset value cannot be read right after reset as all interrupts are masked, i.e. the xpr interrupt remains internally stored and can only be read as soon as the corresponding mask bit is set to 0. 76543210 rme rpf rfo xpr xmr xdu r(0) r(0) rme receive message end 0 = inactive 1 = one complete frame of length less than or equal to the defined block size (exmr.rfbs) or the last part of a frame of length greater than the defined block size has been received. the contents are available in the rfifo. the message length and additional information may be obtained from rbch and rbcl and the rsta register. rpf receive full 0 = inactive 1 = a data block of a frame longer than the defined block size (exmr.rfbs) has been received and is available in the rfifo. the frame is not yet complete. rfo receive frame overflow 0 = inactive 1 = the received data of a frame could not be stored, because the rfifo is occupied. the whole message is lost. this interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to a rpf or rme interrupt (istah). xpr transmit pool ready 0 = inactive pef 81912/81913 register description data sheet 170 2001-03-30 1 = a data block of up to the defined block size (exmr.xfbs) can be written to the xfifo. a xpr interrupt will be generated in the following cases: ? after a xtf or xme command as soon as the 16 / 32 bytes in the xfifo are available and the frame is not yet complete. ? after a xtf together with a xme command is issued, when the whole frame has been transmitted. ? after reset ? after xres xmr transmit message repeat 0 = inactive 1 = the transmission of the last frame has to be repeated because a collision on the s bus has been detected after the 16 th /32 nd data byte of a transmit frame. if a xmr interrupt occurs the transmit fifo is locked until the xmr interrupt is read by the host (interrupt cannot be read if masked in maskh). xdu transmit data underrun 0 = inactive 1 = the current transmission of a frame is aborted by transmitting seven 1s because the xfifo holds no further data. this interrupt occurs whenever the microcontroller has failed to respond to a xpr interrupt (istah register) quick enough, after having initiated a transmission and the message to be transmitted is not yet complete. if a xmr interrupt occurs the transmit fifo is locked until the xdu interrupt is read by the host (interrupt cannot be read if masked in maskh). pef 81912/81913 register description data sheet 171 2001-03-30 4.6.4 maskh - mask register hdlc maskh write address: 20 h value after reset: fc h each interrupt source in the istah register can be selectively masked by setting the corresponding bit in maskh to 1. masked interrupt status bits are not indicated when istah is read. instead, they remain internally stored and pending, until the mask bit is reset to 0. 4.6.5 star - status register star read address: 21 h value after reset: 40 h 76543210 rme rpf rfo xpr xmr xdu 0 0 bit 0..7 mask bits 0 = interrupt active 1 = interrupt masked 76543210 xdov xfw r(0) r(0) raci r(0) xaci 0 xdov transmit data overflow 0 = no transmit data overflow 1 = more than the selected block size of 16 or 32 bytes have been written into the xfifo, i.e. data has been overwritten. xfw transmit fifo write enable 0 = data can not be written in the xfifo pef 81912/81913 register description data sheet 172 2001-03-30 4.6.6 cmdr - command register cmdr write address: 21 h value after reset: 00 h 1 = data can be written in the xfifo. this bit may be polled instead of (or in addition to) using the xpr interrupt. raci receiver active indication 0 = the hdlc receiver is not active 1 = the hdlc receiver is active when raci = 1. this bit may be polled. the raci bit is set active after a begin flag has been received and is reset after receiving an abort sequence. xaci transmitter active indication 0 = the hdlc-transmitter is not active 1 = the hdlc-transmitter is active when xaci = 1. this bit may be polled. the xaci-bit is active when a xtf-command is issued and the frame has not been completely transmitted. 76543210 rmc rres 0 sti xtf 0 xme xres rmc receive message complete 0 = inactive 1 = reaction to rpf (receive pool full) or rme (receive message end) interrupt. by setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the rfifo may be released. rres receiver reset 0 = inactive 1 = hdlc receiver is reset, the rfifo is cleared of any data. sti start timer 0 = inactive pef 81912/81913 register description data sheet 173 2001-03-30 all of these bits must not be set twice within one bcl clock cycle. note: after a xpr interrupt further data has to be written to the xfifo and the appropriate transmit command (xtf) has to be written to the cmdr register again to continue transmission, when the current frame is not yet complete (see also xpr in istah). during frame transmission, the 0-bit insertion according to the hdlc bit-stuffing mechanism is done automatically except in extended transparent mode. 1 = the q-smint ? ix hardware timer is started (see timr register). xtf transmit transparent frame 0 = inactive 1 = after having written up to 16 or 32 bytes (exmr.xfbs) in the xfifo, the microcontroller initiates the transmission of a transparent frame by setting this bit to 1. the opening flag is automatically added to the message by the q-smint ? ix except in the extended transparent mode. xme transmit message end 0 = inactive 1 = by setting this bit to 1 the microcontroller indicates that the data block written last in the xfifo completes the corresponding frame. the q-smint ? ix completes the transmission by appending the crc (if xcrc = 0) and the closing flag sequence to the data except in the extended transparent mode. xres transmitter reset 0 = inactive 1 = hdlc transmitter is reset and the xfifo is cleared of any data. this command can be used by the microcontroller to abort a frame currently in transmission. pef 81912/81913 register description data sheet 174 2001-03-30 4.6.7 modeh - mode register hdlc controller modeh read/write address: 22 h value after reset: c0 h 70 mds2 mds1 mds0 r(0) rac dim2 dim1 dim0 mds2-0 mode select determines the message transfer mode of the hdlc controller, as follows : mds2-0 mode address comparison remark 1.byte 2.byte 0 0 0 reserved C C C 0 0 1 reserved C C C 0 1 0 non-auto mode/8 tei1,tei2 C one-byte address compare. 0 1 1 non-auto mode/16 sap1,sap2, sapg tei1,tei2, teig two-byte address compare. 1 0 0 extended transparent mode CCC 1 1 0 transparent mode 0 C C no address compare. all frames accepted. 1 1 1 transparent mode 1 sap1,sap2, sapg C high-byte address compare. 1 0 1 transparent mode 2 C tei1,tei2, teig low-byte address compare. pef 81912/81913 register description data sheet 175 2001-03-30 4.6.8 exmr - extended mode register exmr read/write address: 23 h value after reset: 00 h note: sap1, sap2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); sapg = fixed value fc / fe h . tei1, tei2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; teig = fixed value ff h . two different methods of the high byte and/or low byte address comparison can be selected by setting sap1.mha and/or sap2.mla (see also description of these bits in chapter 4.6.10 or chapter 4.6.11 respectively). rac receiver active 0 = the hdlc data is not evaluated in the receiver 1 = the hdlc receiver is activated dim2-0 digital interface modes these bits define the characteristics of the iom data ports (du, dd). the dim0 bit enables/disables the stop/go bit (s/g) evaluation. the dim1 bit enables/disables the tic bus access. the effect of the individual dim bits is as follows: 0-0 = stop/go bit evaluation is disabled 0-1 = stop/go bit evaluation is enabled 00- = tic bus access is enabled 01- = tic bus access is disabled 1xx = reserved 70 xfbs rfbs sra xcrc rcrc r(0) itf xfbs transmit fifo block size 0 = block size for the transmit fifo data is 32 byte pef 81912/81913 register description data sheet 176 2001-03-30 1 = block size for the transmit fifo data is 16 byte note: a change of xfbs will take effect after a transmitter command (cmdr.xme, cmdr.xres, cmdr.xtf) has been written. rfbs receive fifo block size 00 = 32 byte 01 = 16 byte 10 = 8 byte 11 = 4 byte note: a change of rfbs will take effect after a receiver command (cmdr.rmc, cmdr.rres) has been written. sra store receive address 0 = receive address is not stored in the rfifo 1 = receive address is stored in the rfifo xcrc transmit crc 0 = crc is transmitted 1 = crc is not transmitted rcrc receive crc 0 = crc is not stored in the rfifo 1 = crc is stored in the rfifo itf interframe time fill selects the inter-frame time fill signal which is transmitted between hdlc- frames. 0 = idle (continuous 1) 1 = flags (sequence of patterns: 0111 1110) note: itf must be set to 0 for power down mode. in applications with d-channel access handling (collision resolution), the only possible inter-frame time fill is idle (continuous 1). otherwise the d-channel on the s/t-bus cannot be accessed. pef 81912/81913 register description data sheet 177 2001-03-30 4.6.9 timr - timer register timr read/write address: 24 h value after reset: 00 h 4.6.10 sap1 - sapi1 register sap1 write address: 25 h value after reset: fc h 754 0 cnt value cnt cnt together with value determines the time period t after which a tin interrupt (ista) will be generated in the normal case: cnt=0...6: t = cnt x 2.048 sec + t1 with t1 = (value+1) x 0.064 sec cnt=7: t = t1 = (value+1) x 0.064 sec (generated periodically) the timer can be started by setting the sti-bit in cmdr and will be stopped when a tin interrupt is generated or the timr register is written. note: if cnt is set to 7, a tin interrupt is indefinitely generated after every expiration of t = t1. value determines the time period t1 t1 = (value + 1) 0.064 sec 70 sapi1 0 mha sapi1 sapi1 value value of the programmable high address byte. in isdn ladp protocol (d- channel) this is the service access point identifier (sapi) and for b-channel applications it is the rah value. pef 81912/81913 register description data sheet 178 2001-03-30 4.6.11 sap2 - sapi2 register sap2 write address: 26 h value after reset: fc h mha mask high address 0 = the high address of an incoming frame is compared with sap1, sap2 and sapg. 1 = the high address of an incoming frame is compared with sap1 and sapg. sap1 can be masked with sap2. bit positions of sap1 are not compared if they are set to 1 in sap2. 70 sapi2 0 mla sapi2 sapi2 value value of the programmable high address byte. in isdn ladp protocol (d- channel) this is the service access point identifier (sapi) and for b-channel applications it is the ral value. mla mask low address 0 = the tei address of an incoming frame is compared with tei1, tei2 and teig. 1 = the tei address of an incoming frame is compared with tei1 and teig. tei1 can be masked with tei2. bit positions of tei1 are not compared if they are set to 1 in tei2. pef 81912/81913 register description data sheet 179 2001-03-30 4.6.12 rbcl - receive frame byte count low rbcl read address: 26 h value after reset: 00 h 4.6.13 rbch - receive frame byte count high for d-channel rbch read address: 27 h value after reset: 00 h . note: normally rbch and rbcl should be read by the microcontroller after a rme- interrupt, in order to determine the number of bytes to be read from the rfifo, and the total message length. the contents of the registers are valid only after a rme or rpf interrupt, and remain so until the frame is acknowledged via the rmc bit or rres. 70 rbc7 rbc0 rbc7-0 receive byte count eight least significant bits of the total number of bytes in a received message (see rbch register). 70 r(0) r(0) r(0) ov rbc11 rbc8 ov overflow 0 = message shorter than (2 12 C 1) = 4095 bytes. 1 = message longer than (2 12 C 1) = 4095 bytes. rbc8-11 receive byte count four most significant bits of the total number of bytes in a received message (see rbcl register). pef 81912/81913 register description data sheet 180 2001-03-30 4.6.14 tei1 - tei1 register tei1 write address: 27 h value after reset: ff h 4.6.15 tei2 - tei2 register tei2 write address: 28 h value after reset: ff h 70 tei1 ea1 tei1 terminal endpoint identifier in all message transfer modes except for transparent modes 0, 1 and extended transparent mode, tei1 is used by the q-smint ? ix for address recognition. in the case of a two-byte address field, it contains the value of the first programmable terminal endpoint identifier according to the isdn lapd-protocol. ea1 address field extension bit this bit is set to 1 according to hdlc/lapd. 70 tei2 ea2 tei2 terminal endpoint identifier in all message transfer modes except in transparent modes 0, 1 and extended transparent mode, tei2 is used by the q-smint ? ix for address recognition. in the case of a two-byte address field, it contains the value of the second programmable terminal endpoint identifier according of the isdn lapd-protocol. pef 81912/81913 register description data sheet 181 2001-03-30 4.6.16 rsta - receive status register rsta read address: 28 h value after reset: 0f h ea2 address field extension bit this bit is to be set to 1 according to hdlc/lapd. 70 vfr rdo crc rab sa1 sa0 c/r ta vfr valid frame determines whether a valid frame has been received. a frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). 0 = the frame is invalid 1 = the frame is valid rdo receive data overflow 0 = no receive data overflow 1 = at least one byte of the frame has been lost, because it could not be stored in rfifo. as opposed the istah.rfo a rdo indicates that the beginning of a frame has been received but not all bytes could be stored as the rfifo was temporarily full. crc crc check 0 = the crc is incorrect 1 = the crc is correct rab receive message aborted 0 = the receive message was not aborted 1 = the receive message was aborted by the remote station, i.e. a sequence of seven 1s was detected before a closing flag. pef 81912/81913 register description data sheet 182 2001-03-30 sa1-0 sapi address identification ta tei address identification these bits are only relevant in modes with address comparison. the result of the address comparison is given by sa1-0 and ta, as follows: note: if sap1 and sap2 contain identical values, the combination sap1,2-teig will only be indicated by sap1,0 = 10 (i.e. the value 00 will not occur in this case). c/r command/response the c/r bit contains the c/r bit of the received frame (bit1 in the sapi address). note: the contents of rsta corresponds to the last received hdlc frame; it is duplicated into rfifo for every frame (last byte of frame). address match with mds2-0 sa1 sa0 ta 1 st byte 2 nd byte 010 (non-auto/8 mode) x x x x 0 1 tei2 tei1 - - 011 (non-auto/16 mode) 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 sap2 sap2 sapg sapg sap1 sap1 teig tei2 teig tei1 or tei2 teig tei1 111 (transparent mode 1) 0 0 1 0 1 0 x x x sap2 sapg sap1 - - - 101 (transparent mode 2) - - - - 0 1 - - teig tei1 or tei2 11x reserved pef 81912/81913 register description data sheet 183 2001-03-30 4.6.17 tmh -test mode register hdlc tmh read/write address: 29 h value after reset: 00 h note: the bits7-1 have to be set to 0. 4.6.18 cir0 - command/indication receive 0 cir0 read address: 2e h value after reset: f3 h 70 r(0) r(0) r(0) r(0) r(0) r(0) r(0) tlp tlp test loop 0 = inactive 1 = the tx path of the hdlc controller is internally connected to its rx path. data coming from the iom-2 will not be forwarded to the hdlc controller. setting of tlp is only valid if iom-2 is active. 70 codr0 cic0 cic1 s/g bas codr0 c/i0 code receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 c/i0 code change 0 = no change in the received command/indication code has been recognized pef 81912/81913 register description data sheet 184 2001-03-30 note: the codr0 bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code are made available in cir0 at the first and second read of that register. 4.6.19 cix0 - command/indication transmit 0 cix0 write address: 2e h value after reset: fe h 1 = a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. cic1 c/i1 code change 0 = no change in the received command/indication code has been recognized 1 = a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. s/g stop/go bit monitoring indicates the availability of the upstream d-channel; 0 = go 1 = stop bas bus access status indicates the state of the tic-bus: 0 = the q-smint ? ix itself occupies the d- and c/i-channel 1 = another device occupies the d- and c/i-channel 70 codx0 tba2 tba1 tba0 bac pef 81912/81913 register description data sheet 185 2001-03-30 4.6.20 cir1 - command/indication receive 1 cir1 read address: 2f h value after reset: fe h codx0 c/i0-code transmit code to be transmitted in the c/i-channel 0. the code is only transmitted if the tic bus is occupied, otherwise 1s are transmitted. tba2-0 tic bus address defines the individual address for the q-smint ? ix on the iom bus. this address is used to access the c/i- and d-channel on the iom interface. note: if only one device is liable to transmit in the c/i- and d-channels of the iom it should always be given the address value 7. bac bus access control only valid if the tic-bus feature is enabled (mode:dim2-0). 0 = inactive 1 = the q-smint ? ix will try to access the tic-bus to occupy the c/i- channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the q-smint ? ix with tic-bus address (tba2-0, cix0 register) 7, which has the lowest priority in a bus configuration. 70 codr1 cicw ci1e codr1 c/i1-code receive cicw c/i-channel width contains the read back value from cix1 register (see below) 0 = 4 bit c/i1 channel width 1 = 6 bit c/i1 channel width pef 81912/81913 register description data sheet 186 2001-03-30 4.6.21 cix1 - command/indication transmit 1 cix1 write address: 2f h value after reset: fe h 4.7 detailed s-transceiver registers 4.7.1 s_conf0 - s-transceiver configuration register 0 s_ conf0 read/write address: 30 h value after reset: 40 h ci1e c/i1-channel interrupt enable contains the read back value from cix1 register (see below) 0 = interrupt generation ista.cic of cir0.cic1is masked 1 = interrupt generation ista.cic of cir0.cic1 is enabled 70 codx1 cicw ci1e codx1 c/i1-code transmit bits 5-0 of c/i-channel 1 cicw c/i-channel width 0 = 4 bit c/i1 channel width 1 = 6 bit c/i1 channel width the c/i1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. however, in write direction the full codx1 code is transmitted, i.e. the host must write the higher two bits to 1. ci1e c/i1-channel interrupt enable 0 = interrupt generation ista.cic of cir0.cic1is masked 1 = interrupt generation ista.cic of cir0.cic1 is enabled pef 81912/81913 register description data sheet 187 2001-03-30 70 dis_tr bus en_ icv 0 l1sw 0 exlp 0 dis_tr disable transceiver 0 = all s-transceiver functions are enabled. 1 = all s-transceiver functions are disabled and powered down (analog and digital parts). bus point-to-point / bus selection 0 = adaptive timing (point-to-point, extended passive bus). 1 = fixed timing (short passive bus), directly derived from transmit clock. en_icv enable far end code violation 0 = normal operation. 1 = icv enabled. the receipt of at least one illegal code violation within one multi-frame according to ansi t1.605 is indicated by the c/i indication 1011 (cvr) in two consecutive iom frames. l1sw enable layer 1 state machine in software 0 = layer 1 state machine of the q-smint ? ix is used. 1 = layer 1 state machine is disabled. the functionality must be realized in software. the commands are written to register s_cmd and the status read in the s_sta. exlp external loop in case the analog loopback is activated with c/i = arl or with the lp_a bit in the s_cmd register the loop is a 0 = internal loop next to the line pins 1 = external loop which has to be closed between sr1/sr2 and sx1/ sx2 note: for the external loop the transmitter must be enabled (s_conf2:dis_tx = 0). pef 81912/81913 register description data sheet 188 2001-03-30 4.7.2 s_conf2 - s-transmitter configuration register 2 s_ conf2 read/write address: 32 h value after reset: 80 h 4.7.3 s_sta - s-transceiver status register s_ sta read address: 33 h value after reset: 00 h important: this register is used only if the layer 1 state machine of the device is disabled (s_conf0:l1sw = 1) and implemented in software! with the layer 1 state machine enabled, the signals from this register are automatically evaluated. 70 dis_tx0000000 dis_tx disable line driver 0 = transmitter is enabled 1 = transmitter is disabled 70 rinf 0 icv 0 fsyn 0 ld rinf receiver info 00 = received info 0 (no signal) 01 = received any signal except info 0 or info 3 10 = reserved 11 = received info 3 icv illegal code violation 0 = no illegal code violation is detected. 1 = illegal code violation (ansi t1.605) in data stream is detected. pef 81912/81913 register description data sheet 189 2001-03-30 4.7.4 s_cmd - s-transceiver command register s_ cmd read/write address: 34 h value after reset: 08 h important: this register - except bit dprio - is writable only if the layer 1 state machine of the device is disabled (s_conf0.l1sw = 1) and implemented in software! with the device layer 1 state machine enabled, the signals from this register are automatically generated. dprio can also be written in intelligent nt mode. fsyn frame synchronization state 0 = the s/t receiver is not synchronized. 1 = the s/t receiver has synchronized to the framing bit f. ld level detection 0 = no receive signal has been detected on the line. 1 = any receive signal has been detected on the line. 70 xinf dprio 1 pd lp_a 0 xinf transmit info 000 = transmit info 0 001 = reserved 010 = transmit info 2 011 = transmit info 4 100 = send continuous pulses at 192 kbit/s alternating or 96 khz rectangular, respectively (tm2) 101 = send single pulses at 4 kbit/s with alternating polarity corresponding to 2 khz fundamental mode (tm1) 11x = reserved dprio d-channel priority 0 = priority class 1 for d channel access on iom pef 81912/81913 register description data sheet 190 2001-03-30 4.7.5 sqrr - s/q-channel receive register sqrr read address: 35 h value after reset: 00 h 1 = priority class 2 for d channel access on iom pd power down 0 = the transceiver is set to operational mode 1 = the transceiver is set to power down mode lp_a loop analog the setting of this bit corresponds to the c/i command arl. 0 = analog loop is open 1 = analog loop is closed internally or externally according to the exlp bit in the s_conf0 register 70 msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 msyn multi-frame synchronization state 0 = the s/t receiver has not synchronized to the received f a and m bits 1 = the s/t receiver has synchronized to the received f a and m bits mfen multiframe enable read-back of the mfen bit of the sqxr register 0 = s/t multiframe is disabled 1 = s/t multiframe is enabled sqr1-4 received s/q bits received q bits in frames 1, 6, 11 and 16 pef 81912/81913 register description data sheet 191 2001-03-30 4.7.6 sqxr- s/q-channel transmit register sqxr write address: 35 h value after reset: 00 h 4.7.7 istas - interrupt status register s-transceiver istas read address: 38 h value after reset: 00 h 70 0 mfen 0 0 sqx1 sqx2 sqx3 sqx4 mfen multiframe enable used to enable or disable the multiframe structure. 0 = s/t multiframe is disabled 1 = s/t multiframe is enabled sqx1-4 transmitted s/q bits transmitted s bits in frames 1, 6, 11 and 16 70 x x x x ld ric sqc sqw these bits are set if an interrupt status occurs and an interrupt signal is activated if the corresponding mask bit is set to 0. if the mask bit is set to 1 no interrupt is generated, however the interrupt status bit is set in istas. ric, sqc and sqw are cleared by reading the corresponding source register s_sta, sqrr or writing sqxr, respectively. x reserved ld level detection pef 81912/81913 register description data sheet 192 2001-03-30 4.7.8 masks - mask s-transceiver interrupt masks read/write address: 39 h value after reset: ff h 0 = inactive 1 = any receive signal has been detected on the line. this bit is set to 1 (i.e. an interrupt is generated if not masked) as long as any receive signal is detected on the line. ric receiver info change 0 = inactive 1 = ric is activated if one of the s_sta bits rinf or icv has changed. sqc s/q-channel change 0 = inactive 1 = a change in the received 4-bit q-channel has been detected. the new code can be read from the sqrx bits of registers sqrr within the next multiframe 1) . this bit is reset by a read access to the sqrr register. sqw s/q-channel writable 0 = inactive 1 = the s channel data for the next multiframe is writable. the register for the s bits to be transmitted has to be written within the next multiframe. this bit is reset by writing register sqxr. this timing signal is indicated with the start of every multiframe. data which is written right after sqw-indication will be transmitted with the start of the following multiframe. data which is written before sqw-indication is transmitted in the multiframe which is indicated by sqw. sqw and sqc could be generated at the same time. 1) register sqrr stays valid as long as no code change has been received. 70 1 1 1 1 ld ric sqc sqw pef 81912/81913 register description data sheet 193 2001-03-30 4.7.9 s_mode - s-transceiver mode s_ mode read/write address: 3a h value after reset: 02 h bit 3..0 mask bits 0 = the transceiver interrupts ld, ric, sqc and sqw are enabled 1 = the transceiver interrupts ld, ric, sqc and sqw are masked 70 0 0 0 0 dch_inh mode dch_ inh d-channel inhibit 0 = inactive 1 = the s-transceiver blocks the access to the d-channel on s by inverting the e-bits. mode mode selection 000 = reserved 001 = reserved 010 = nt (without d-channel handler) 011 = lt-s (without d-channel handler) 110 intelligent nt mode (with nt state machine and with d-channel handler) 111 intelligent nt mode (with lt-s state machine and with d-channel handler) 100 reserved 101 reserved pef 81912/81913 register description data sheet 194 2001-03-30 4.8 interrupt and general configuration registers 4.8.1 ista - interrupt status register ista read address: 3c h value after reset: 00 h 70 u st cic tin wov s mos hdlc u u-transceiver interrupt 0 = inactive 1 = an interrupt was generated by the u-transceiver. read the istau register. st synchronous transfer 0 = inactive 1 = this interrupt enables the microcontroller to lock on to the iom ? -2 timing, for synchronous transfers. cic c/i channel change 0 = inactive 1 = a change in c/i0 channel or c/i1 channel has been recognized. the actual value can be read from cir0 or cir1. tin timer interrupt 0 = inactive 1 = the internal timer and repeat counter has expired (see timr register). wov watchdog timer overflow 0 = inactive pef 81912/81913 register description data sheet 195 2001-03-30 note: a read of the ista register clears only the tin and wov interrupts. the other interrupts are cleared by reading the corresponding status register. 4.8.2 mask - mask register mask write address: 3c h value after reset: ff h 1 = signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits wtc1 and wtc2 (mode1 register) in the correct manner. a reset out pulse on pin rsto has been generated by the q-smint ? ix. s s-transceiver interrupt 0 = inactive 1 = an interrupt was generated by the s-transceiver. read the istas register. mos monitor status 0 = inactive 1 = a change in the monitor status register (mosr) has occurred. hdlc hdlc interrupt 0 = inactive 1 = an interrupt originated in the hdlc interrupt sources has been recognized. 70 u st cic tin wov s mos hdlc bit 7..0 mask bits 0 = interrupt is not masked 1 = interrupt is masked pef 81912/81913 register description data sheet 196 2001-03-30 each interrupt source in the ista register can be selectively masked by setting the corresponding bit in mask to 1. masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to 0. note: in the event of a c/i channel change, cic is set in ista even if the corresponding mask bit in mask is active, but no interrupt is generated. 4.8.3 mode1 - mode1 register mode1 read/write address: 3d h value after reset: 04 h 70 mclk cds wtc1 wtc2 cfs rss2 rss1 mclk master clock frequency the master clock frequency bits control the microcontroller clock output depending on mode1.cds = 0 or 1 (table table 2.1.3 ). mode1.cds = 0 mode1.cds = 1 00 = 3.84 mhz 7.68 mhz 01 = 0.96 mhz 1.92 mhz 10 = 7.68 mhz 15.36 mhz 11 = disabled disabled cds clock divider selection 0 = the 15.36 mhz oscillator clock divided by two is input to the mclk prescaler 1 = the 15.36 mhz oscillator clock is input to the mclk prescaler. wtc1, 2 watchdog timer control 1, 2 after the watchdog timer mode has been selected (rss = 11) the watchdog timer is started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bit in the following sequence ( chapter 2.2 ): 10 first step pef 81912/81913 register description data sheet 197 2001-03-30 4.8.4 mode2 - mode2 register mode2 read/write address: 3e h value after reset: 00 h 01 second step to reset and restart the watchdog timer. if not, the timer expires and a wov-interrupt (ista register) together with a reset out pulse on pin rsto is generated. the watchdog timer runs only when the internal iom ? -2 clocks are active, i.e. the watchdog timer is dead when bit cfs = 1 and the u and s- transceivers are in state power down. cfs configuration select 0 = the iom ? -2 interface clock and frame signals are always active, deactivated state of the u-transceiver and the s-transceiver included. 1 = the iom ? -2 interface clocks and frame signals are inactive in the deactivated state of the u-transceiver and the s-transceiver. rss2, rss1 reset source selection 2,1 the q-smint ? ix reset sources can be selected according to the table below. c/i code change watchdog timer por/uvd and rst 00 =----x 01 = rsto disabled (high impedance) 10 = x -- x 11 = -- x x 70 led2 led1 ledc 0 0 0 amod ppsdx led2,1 led control on pin act 00 = high pef 81912/81913 register description data sheet 198 2001-03-30 4.8.5 id - identification register id read address: 3f h value after reset: 01 h 01 = flashing at 8 hz 10 = flashing at 1 hz 11 = low ledc led control enable 0 = led is controlled by the state machines as defined in table 4 . 1 = led is controlled via bits led2,1. amod address mode selects between direct and indirect register access of the parallel microcontroller interface. 0 = indirect address mode is selected. the address line a0 is used to select between address (a0 = 0) and data (a0 = 1) register 1 = direct address mode is selected. the address is applied to the address bus (a0-a6) ppsdx push/pull output for sdx 0 = the sdx pin has open drain characteristic 1 = the sdx pin has push/pull characteristic 70 0 0 design pef 81912/81913 register description data sheet 199 2001-03-30 4.8.6 sres - software reset register sres write address: 3f h value after reset: 00 h 4.9 detailed iom ? -2 handler registers 4.9.1 cdaxy - controller data access register xy these registers are used for microcontroller access to the iom ? -2 timeslots as well as for timeslot manipulations. (e.g. loops, shifts, ... see also controller data access (cda) on page 31 ). design design number the design number (design) allows to identify different hardware designs 1) of the q-smint ? ix by software. 000000: version 1.1 000001: version 1.2 000001: version 1.3 1) distinction of different firmware versions is also possible by reading register (7d) h in the address space of the u-transceiver (see chapter 4.11.19 ). 70 00res_ ci/tic 0 res_ hdlc 0 res_s res_u res_xx reset_xx 0 = deactivates the reset of the functional block xx 1 = activates the reset of the functional block xx. the reset state is activated as long as the bit is set to 1 pef 81912/81913 register description data sheet 200 2001-03-30 cdaxy read/write address: 40-43 h data register cdaxy which can be accessed by the controller. 4.9.2 xxx_tsdpxy - time slot and data port selection for chxy xxx_tsdpxy read/write address: 44-4d h this register determines the time slots and the data ports on the iom ? -2 interface for the data channels xy of the functional units xxx (controller data access (cda) and s- transceiver (s)). note: the u-transceiver is always in iom-2 channel 0. 70 controller data access register register value after reset register address cda10 ff h 40 h cda11 ff h 41 h cda20 ff h 42 h cda21 ff h 43 h 70 dps000 tss register value after reset register address cda_tsdp10 00 h (= output on b1-dd) 44 h cda_tsdp11 01 h (= output on b2-dd) 45 h cda_tsdp20 80 h (= output on b1-du) 46 h cda_tsdp21 81 h (= output on b2-du) 47 h reserved 48-4b h s_tsdp_b1 84 h (= output on ts4-du) 4c h s_tsdp_b2 85 h (= output on ts5-du) 4d h pef 81912/81913 register description data sheet 201 2001-03-30 4.9.3 cdax_cr - control register controller data access ch1x cdax_cr read/write address: 4e-4f h dps data port selection 0 = the data channel xy of the functional unit xxx is output on dd. the data channel xy of the functional unit xxx is input from du. 1 = the data channel xy of the functional unit xxx is output on du. the data channel xy of the functional unit xxx is input from dd. note: for the cda (controller data access) data the input is determined by the cdax_cr.swap bit. if swap = 0 the input for the cdaxy data is vice versa to the output setting for cdaxy. if the swap = 1 the input from cdax0 is vice versa to the output setting of cdax1 and the input from cdax1 is vice versa to the output setting of cdax0. tss timeslot selection selects one of the 12 timeslots from 0...11 on the iom ? -2 interface for the data channels. 70 0 0 en_tbm en_i1 en_i0 en_o1 en_o0 swap register value after reset register address cda1_cr 00 h 4e h cda2_cr 00 h 4f h en_tbm enable tic bus monitoring 0 = the tic bus monitoring is disabled 1 = the tic bus monitoring with the cdax0 register is enabled. the tsdpx0 register must be set to 08 h for monitoring from du, or 88 h for monitoring from dd. en_i1, en_i0 enable input cdax1, cdax0 pef 81912/81913 register description data sheet 202 2001-03-30 4.9.4 s_cr - control register s-transceiver data s_cr read/write address: 51 h value after reset: ff h 0 = the input of the cdax1, cdax0 register is disabled 1 = the input of the cdax1, cdax0 register is enabled en_o1, en_o0 enable output cdax1, cdax0 0 = the output of the cdax1, cdax0 register is disabled 1 = the output of the cdax1, cdax0 register is enabled swap swap inputs 0 = the time slot and data port for the input of the cdaxy register is defined by its own tsdpxy register. the data port for the cdaxy input is vice versa to the output setting for cdaxy. 1 = the input (time slot and data port) of the cdax0 is defined by the tsdp register of cdax1 and the input of cdax1 is defined by the tsdp register of cdax0. the data port for the cdax0 input is vice versa to the output setting for cdax1. the data port for the cdax1 input is vice versa to the output setting for cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 to cdax0. the outputs are not affected by the swap bit. 70 1 ci_cs en_d en_b2r en_b1r en_b2x en_b1x d_cs ci_cs c/i channel selection this bit is used to select the iom channel to which the s-transceiver c/i- channel is related to. 0 = c/i-channel in iom-channel 0 1 = c/i-channel in iom-channel 1 pef 81912/81913 register description data sheet 203 2001-03-30 en_d enable transceiver d-channel data 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b2r enable transceiver b2 receive data (transmitter receives from iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b1r enable transceiver b1 receive data (transmitter receives from iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b2x enable transceiver b2 transmit data (transmitter transmits to iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b1x enable transceiver b1 transmit data (transmitter transmits to iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. these bits are used to individually enable/disable the d-channel and the receive/transmit paths for the b-channels for the s-transceiver. d_cs d channel selection this bit is used to select the iom channel to which the s-transceiver d- channel is related to. 0 = d-channel in iom-channel 0 1 = d-channel in iom-channel 1 pef 81912/81913 register description data sheet 204 2001-03-30 4.9.5 hci_cr - control register for hdlc and ci1 data hci_cr read/write address: 52 h value after reset: 04 h 70 dps_ci1 en_ci1 en_d en_b2h en_b1h dps_h hcs dps_ci1 data port selection ci1 handler 0 = the ci1 data is output on dd and input from du 1 = the ci1 data is output on du and input from dd en_ci1 enable ci1 handler 0 = ci1 data access is disabled 1 = ci1 data access is enabled note: the timeslot for the c/i1 handler cannot be programmed but is fixed to iom channel 1. en_d enable d-timeslot for hdlc controller 0 = the hdlc controller does not access timeslot data d 1 = the hdlc controller does access timeslot data d en_b2h enable b2-timeslot for hdlc controller 0 = the hdlc controller does not access timeslot data b2 1 = the hdlc controller does access timeslot data b2 en_b1h enable b1-timeslot for hdlc controller 0 = the hdlc controller does not access timeslot data b1 respectively 1 = the hdlc controller does access timeslot data b1 the bits en_d, en_b2h and en_b1h are used to select the timeslot length for the d- channel hdlc controller access as it is capable to access not only the d-channel timeslot. the host can individually enable two 8-bit timeslots b1- and b2-channel, i.e. the first and second octett, (en_b1h, en_b2h) and one 2-bit timeslot d-channel (en_d) on iom-2. the position is selected via hcs. pef 81912/81913 register description data sheet 205 2001-03-30 4.9.6 mon_cr - control register monitor data mon_cr read/write address: 53 h value after reset: 40 h dps_h data port selection hdlc 0 = transmit on dd, receive on du 1 = transmit on du, receive on dd hcs hdlc channel selection these two bits determine the iom ? -2 channel of the hdlc controller. the hdlc controller will read and write hdlc data into the selected b1, b2 and d channel timeslots of the selected iom ? -2 channel. 00 = the hdlc data is read and output on iom-channel 0 01 = the hdlc data is read and output on iom-channel 1 10 = the hdlc data is read and output on iom-channel 2 1) 11 = not defined 1) if the tic-bus is enabled, then an hdlc access in iom-channel 2 is possible only to the b channels. 70 dps en_mon 0 0 0 0 mcs dps data port selection 0 = the monitor data is output on dd and input from du 1 = the monitor data is output on du and input from dd en_mon enable output 0 = the monitor data input and output is disabled 1 = the monitor data input and output is enabled mcs monitor channel selection 00 = the monitor data is output on mon0 01 = the monitor data is output on mon1 pef 81912/81913 register description data sheet 206 2001-03-30 4.9.7 sds1_cr - control register serial data strobe 1 sds1_cr read/write address: 54 h value after reset: 00 h this register is used to select position and length of the strobe signal 1. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). 10 = the monitor data is output on mon2 11 = not defined 70 ens_ tss ens_ tss+1 ens_ tss+3 0tss ens_ tss enable serial data strobe of timeslot tss 0 = the serial data strobe signal sds1 is inactive during tss 1 = the serial data strobe signal sds1 is active during tss ens_ tss+1 enable serial data strobe of timeslot tss+1 0 = the serial data strobe signal sds1 is inactive during tss+1 1 = the serial data strobe signal sds1 is active during tss+1 ens_ tss+3 enable serial data strobe of timeslot tss+3 (d-channel) 0 = the serial data strobe signal sds1 is inactive during the d-channel (bit7, 6) of tss+3 1 = the serial data strobe signal sds1 is active during the d-channel (bit7, 6) of tss+3 tss timeslot selection selects one of 12 timeslots on the iom ? -2 interface (with respect to fsc) during which sds1 is active high. the data strobe signal allows standard data devices to access a programmable channel. pef 81912/81913 register description data sheet 207 2001-03-30 4.9.8 sds2_cr - control register serial data strobe 2 sds2_cr read/write address: 55 h value after reset: 00 h this register is used to select position and length of the strobe signal 2. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). 70 ens_ tss ens_ tss+1 ens_ tss+3 0tss ens_ tss enable serial data strobe of timeslot tss 0 = the serial data strobe signal sds2 is inactive during tss 1 = the serial data strobe signal sds2 is active during tss ens_ tss+1 enable serial data strobe of timeslot tss+1 0 = the serial data strobe signal sds2 is inactive during tss+1 1 = the serial data strobe signal sds2 is active during tss+1 ens_ tss+3 enable serial data strobe of timeslot tss+3 (d-channel) 0 = the serial data strobe signal sds2 is inactive during the d-channel (bit7, 6) of tss+3 1 = the serial data strobe signal sds2 is active during the d-channel (bit7, 6) of tss+3 tss timeslot selection selects one of 12 timeslots on the iom ? -2 interface (with respect to fsc) during which sds2 is active high. the data strobe signal allows standard data devices to access a programmable channel. pef 81912/81913 register description data sheet 208 2001-03-30 4.9.9 iom_cr - control register iom data iom_cr read/write address: 56 h value after reset: 08 h 70 spu 0 0 tic_dis en_bcl 0 dis_od dis_iom spu software power up 0 = the du line is normally used for transmitting data. 1 = setting this bit to 1 will pull the du line to low. this will enforce the q-smint ? ix and other connected layer 1 devices to deliver iom- clocking. tic_dis tic bus disable 0 = the last octet of the last iom time slot (ts 11) is used as tic bus. 1 = the tic bus is disabled. the last octet of the last iom time slot (ts 11) can be used like any other time slot. this means that the timeslots tic, a/b, s/g and bac are not available any more. en_bcl enable bit clock bcl 0 = the bcl clock is disabled (output is high impedant) 1 = the bcl clock is enabled dis_od disable open drain 0 = iom outputs are open drain driver 1 = iom outputs are push pull driver dis_iom disable iom dis_iom should be set to 1 if external devices connected to the iom interface should be disconnected e.g. for power saving purposes. however, the q-smint ? ix internal operation is independent of the dis_iom bit. pef 81912/81913 register description data sheet 209 2001-03-30 4.9.10 mcda - monitoring cda bits mcda read address: 57 h value after reset: ff h 4.9.11 sti - synchronous transfer interrupt sti read address: 58 h value after reset: 00 h 0 = the iom interface is enabled 1 = the iom interface is disabled (fsc, dcl, clock outputs have high impedance; du, dd data line inputs are switched off and outputs are high impedant) 70 mcda21 mcda20 mcda11 mcda10 bit7 bit6 bit7 bit6 bit7 bit6 bit7 bit6 mcdaxy monitoring cdaxy bits bit 7 and bit 6 of the cdaxy registers are mapped into the mcda register. this can be used for monitoring the d-channel bits on du and dd and the echo bits on the tic bus with the same register. 70 stov21 stov20 stov11 stov10 sti21 sti20 sti11 sti10 for all interrupts in the sti register the following logical states are applied 0 = interrupt has not occurred 1 = interrupt has occurred stovxy synchronous transfer overflow interrupt pef 81912/81913 register description data sheet 210 2001-03-30 note: st0vxy and ackxy are useful for synchronizing microcontroller accesses and receive/transmit operations. one bcl clock is equivalent to two dcl clocks. 4.9.12 asti - acknowledge synchronous transfer interrupt asti write address: 58 h value after reset: 00 h 4.9.13 msti - mask synchronous transfer interrupt msti read/write address: 59 h value after reset: ff h enabled stov interrupts for a certain stixy interrupt are generated when the stixy has not been acknowledged in time via the ackxy bit in the asti register. this must be one (for dps = 0) or zero (for dps = 1) bcl clock cycles before the time slot which is selected for the stov. stixy synchronous transfer interrupt depending on the dps bit in the corresponding tsdpxy register the synchronous transfer interrupt stixy is generated two (for dps = 0) or one (for dps = 1) bcl clock cycles after the selected time slot (tsdpxy.tss). 70 0 0 0 0 ack21 ack20 ack11 ack10 ackxy acknowledge synchronous transfer interrupt after a stixy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ackxy bit. 0 = no activity is initiated 1 = sets the acknowledge bit ackxy for a stixy interrupt 70 stov21 stov20 stov11 stov10 sti21 sti20 sti11 sti10 pef 81912/81913 register description data sheet 211 2001-03-30 4.10 detailed monitor handler registers 4.10.1 mor - monitor receive channel mor read address: 5c h value after reset: ff h contains the monitor data received in the iom ? -2 monitor channel according to the monitor channel protocol. the monitor channel (0,1,2) can be selected by setting the monitor channel select bit mon_cr.mcs. 4.10.2 mox - monitor transmit channel mox write address: 5c h value after reset: ff h contains the monitor data to be transmitted in iom ? -2 monitor channel according to the monitor channel protocol. the monitor channel (0,1,2) can be selected by setting the monitor channel select bit mon_cr.mcs for the msti register the following logical states are applied: 0 = interrupt is not masked 1 = interrupt is masked stovxy mask synchronous transfer overflow xy mask bits for the corresponding stovxy interrupt bits. stixy synchronous transfer interrupt xy mask bits for the corresponding stixy interrupt bits. 70 70 pef 81912/81913 register description data sheet 212 2001-03-30 4.10.3 mosr - monitor interrupt status register mosr read address: 5d h value after reset: 00 h 4.10.4 mocr - monitor control register mocr read/write address: 5e h value after reset: 00 h 70 mdr mer mda mab 0 0 0 0 mdr monitor channel data received 0 = inactive 1 = monitor channel data received mer monitor channel end of reception 0 = inactive 1 = monitor channel end of reception mda monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. 0 = inactive 1 = monitor channel data acknowledged mab monitor channel data abort 0 = inactive 1 = monitor channel data abort 70 mre mrc mie mxc 0 0 0 0 pef 81912/81913 register description data sheet 213 2001-03-30 4.10.5 msta - monitor status register msta read address: 5f h value after reset: 00 h mre monitor receive interrupt enable 0 = monitor interrupt status mdr generation is masked. 1 = monitor interrupt status mdr generation is enabled. mrc mr bit control determines the value of the mr bit: 0 = mr is always 1. in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1 = mr is internally controlled by the q-smint ? ix according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1). mie monitor interrupt enable 0 = monitor interrupt status mer, mda, mab generation is masked 1 = monitor interrupt status mer, mda, mab generation is enabled mxc mx bit control determines the value of the mx bit: 0 = the mx bit is always 1. 1 = the mx bit is internally controlled by the q-smint ? ix according to monitor channel protocol. 70 00000mac0tout mac monitor transmit channel active 0 = no data transmission in the monitor channel pef 81912/81913 register description data sheet 214 2001-03-30 4.10.6 mconf - monitor configuration register mconf write address: 5f h value after reset: 00 h 4.11 detailed u-transceiver registers 4.11.1 opmode - operation mode register the op eration mode register determines the operating mode of the u-transceiver. opmode read* ) / write address: 60 h reset value: 14 h 1 = the data transmission in the monitor channel is in progress. tout time-out read-back value of the tout bit 0 = the monitor time-out function is disabled 1 = the monitor time-out function is enabled 70 0000000tout tout time-out 0 = the monitor time-out function is disabled 1 = the monitor time-out function is enabled 76543210 0 uci febe mlt 0 ci_sel 0 0 uci enable/disable m c control of c/i codes pef 81912/81913 register description data sheet 215 2001-03-30 4.11.2 mfilt - m bit filter options the m bit filter register defines the validation algorithm received maintenance channel bits (eoc, m4, m56) of the u-interface have to undergo before they are approved and passed on to the c. mfilt read* ) / write address: 61 h reset value: 14 h 0= m c control disabled - c/i codes are exchanged via iom ? -2 read access to register ucir by the m p is still possible 1= m c control enabled - c/i codes are exchanged via ucir and uciw registers in this case, the according c/i-channel on iom ? -2 is idle 1111 febe enable/disable external write access to febe bit in register m56w 0 = external access to febe bit disabled - febe bit is controlled by internal febe counter 1 = external access to febe bit enabled - febe bit is controlled by external microprocessor mlt enable/disable metallic loop termination function mlt status is reflected in bit ms2 and ms1 in register m56r 0 = mlt disabled 1 = mlt enabled ci_sel c/i code output selection by ci_sel the user can switch: C between the standard c/i indications of the nt state machine as implemented in todays iec-q versions or C newly defined c/i code indications which facilitates control and debugging 0 = standard nt state machine compliant to nt state machine of todays iec-q v4.3-v5.3 1 = simplified nt state machine output of newly defined c/i code indications for enhanced activation/deactivation control and debugging facilities 76543210 pef 81912/81913 register description data sheet 216 2001-03-30 4.11.3 eocr - eoc read register the eoc r ead register contains the last verified eoc message (m1-m3 bits) according to the verification criterion selected in mfilt.eoc filter. eocr read address: 63 h reset value: 0fff h m56 filter m4 filter eoc filter m56 filter controls the validation mode of the spare bits (m51, m52, m61) on a per bit base (see chapter 2.4.4.3 ) . x0 = apply same filter to m5 and m6 bit data as programmed for m4 bit data. x1 = on change m4 filter 3-bit field which controls the validation mode of the m4 bits on a per bit base (see chapter 2.4.4.1 ). x00 = on change x01 = tll coverage of m4 bit data x10 = crc coverage of m4 bit data x11 = crc and tll coverage of m4 bit data 0xx = m4 bits towards state machine are covered by tll. 1xx = m4 bits towards state machine are checked by the same validation algorithm as programmed for the reporting to the system interface (see chapter 2.4.4.2 ). eoc filter 3-bit field which controls the processing of eoc messages and its verification algorithm (see chapter 2.4.3.3 ). 100 = eoc automatic mode 001 = eoc transparent mode without any filtering 010 = eoc transparent mode with on change filtering 011 = eoc transparent mode with triple-last-look (tll) filtering 15 14 13 12 11 10 9 8 pef 81912/81913 register description data sheet 217 2001-03-30 4.11.4 eocw - eoc write register via the eoc w rite register, the eoc message (m1-m3 bits) of the next available u superframe can be sent and it will be repeated until a new value is written to eocw, or the line is deactivated. access to the eocw register is reasonably only if the eoc channel is operated in transparent mode, otherwise conflicts with the internal eoc processor may occur. eocw write address: 65 h reset value: 0100 h 0 0 0 0 a1 a2 a3 d/m 76543210 i1 i2 i3 i4 i5 i6 i7 i8 eoc embedded operations channel (see chapter 2.4.3 ) a1 .. a3 address field d/m data/ message indicator i1 .. i8 information field, 15 14 13 12 11 10 9 8 0 0 0 0 a1 a2 a3 d/m 76543210 i1 i2 i3 i4 i5 i6 i7 i8 a1 .. a3 address field d/m data/ message indicator pef 81912/81913 register description data sheet 218 2001-03-30 4.11.5 m4rmask - m4 read mask register via the m4 read mask register, the user can selectively control which m4 bit changes are reported via interrupt requests. m4rmask read* ) / write address: 67 h reset value: 00 h 4.11.6 m4wmask - m4 write mask register access to the m4 write mask register (m4w) is controlled by the m4wmask register. by means of the m4wmask register the user can control on a per bit base which m4 bits are controlled by the user and which are controlled by the state machine. m4wmask read* ) / write address: 68 h reset value: a8 h i1 .. i8 information field (8 codes are reserved by ansi/etsi for diagnostic and loopback functions) 76543210 m4 read mask bits bit 0..7 0 = m4 bit change indication by interrupt active 1 = m4 bit change indication by interrupt masked 76543210 m4 write mask bits bit 0..7 0 = m4 bit is controlled by state machine/ external pins (ps1,2) 1 = m4 bit is controlled by m c bit 6 partial activation control external/automatic , function corresponds to the mon-8 commands pace and paca pef 81912/81913 register description data sheet 219 2001-03-30 4.11.7 m4r - m4 read the r ead m4 bit register contains the last received and verified m4 bit data. m4r read address: 69 h reset value: be h 0 = sai bit is controlled and uoa bit is evaluated by state machine 1 = sai bit is controlled via the c, uoa=1 is reported to the state machine 76543210 aib uoa m46 m45 m44 sco dea act aib interruption (according to ansi) 0 = indicates interruption 1 = inactive uoa u activation only 0 = indicates that only u is activated 1 = inactive sco start-on-command only bit indicates whether the dlc network will deactivate the loop between calls (defined in bellcore tr-nwt000397) 0 = start-on-command-only mode active, in lult mode the u-transceiver shall initiate the start-up procedure only upon command from the network (ar primitive) 1 = normal mode, if the u-transceiver is operated within a dcl configuration as lult it shall start operation as soon as power is applied dea deactivation bit 0 = lt informs nt that it will turn off 1 = inactive pef 81912/81913 register description data sheet 220 2001-03-30 4.11.8 m4w - m4 write register via the m4 bit w rite register the m4 bits of the next available u-superframe and subsequent ones can be controlled. the value is latched and transmitted until a new value is set. m4w write address: 6a h reset value: be h act activation bit 0 = layer 2 not established 1 = signals layer 2 ready for communication 76543210 nib sai m46 cso ntm ps2 ps1 act nib network indication bit 0 = no function (reserved for network use) 1 = no function (reserved for network use) sai s activity indicator 0 = s-interface is deactivated 1 = s-interface is activated cso cold start only 0 = nt is capable to perform warm starts 1 = nt activation with cold start only ntm nt test mode 0 = nt busy in test mode 1 = inactive ps2 power status secondary source 0 = secondary power supply failed pef 81912/81913 register description data sheet 221 2001-03-30 4.11.9 m56r - m56 read register bits 1 to 3 of the m5, m6 bit r ead register contain the last verified m5, m6 bit information. bits 5 and 6 reflect the current mlt state (ms2,1). the febe/nebe error indication bits are accommodated at bit positions 0 and 4. they signal that a febe and/or nebe error have/has occurred. m56r read address: 6b h reset value: 1f h 1 = secondary power supply ok ps1 power status primary source 0 = primary power supply failed 1 = primary power supply ok act activation bit 0 = layer 2 not established 1 = signals layer 2 ready for communication 76543210 0 ms2 ms1 nebe m61 m52 m51 febe ms1,2 mlt status 00 = normal mode 01 = insertion loss 10 = quiet mode 11 = reserved nebe near-end block error 0 = near-end block error has occurred 1 = no near-end block error has occurred m61, m52, m51 received spare bits of last u superframe (m51, m52 and m61 have no effect on the q-smint ? ix ). pef 81912/81913 register description data sheet 222 2001-03-30 4.11.10 m56w - m56 write register via the m56 bit w rite register, the m5 and m6 bits of the next available superframe can be set. the value is latched and transmitted as long as a new value is set or the function is disabled. the febe bit can only be set and controlled externally if opmode.febe is set to 1. m56w write address: 6c h reset value: ff h 4.11.11 ucir - c/i code read register via the u -transceiver c/i code r ead register a microcontroller can access the c/i code that is output from the state machine. ucir read address: 6d h reset value: 00 h febe far-end block error 0 = far-end block error has occurred 1 = no far-end block error has occurred 76543210 1 1 1 1 m61 m52 m51 febe m61, m52, m51 transmitted spare bits to next u superframe (m51, m52 and m61 have no effect on the q-smint ? ix. febe far-end block error 0 = far-end block error has occurred 1 = no far-end block error has occurred 76543210 0 0 0 0 c/i code output pef 81912/81913 register description data sheet 223 2001-03-30 4.11.12 uciw - c/i code write register the u -transceiver c/i code w rite register allows a microcontroller to control the state of the u-transceiver. to enable this function bit uci in register opmode must be set to 1 before. uciw write address: 6e h reset value: 01 h 4.11.13 test - test register the test register sets the u-transceiver in the desired test mode. test read* ) / write address: 6f h reset value: 00 h 76543210 0 0 0 0 c/i code input 76543210 0000ccrc+-1 tones 0 40khz ccrc send corrupt crc 0 = inactive 1 = send corrupt (inverted) crcs +-1 tones send +/-1 pulses instead of +/-3 0 = issues +/-3 pulses during 40 khz tone generation or in ssp mode 1 = issues +/-1 pulses 40khz 40 khz test signal 0 = issues single pulses in state test 1 = issues a 40 khz test signal in state test pef 81912/81913 register description data sheet 224 2001-03-30 4.11.14 loop - loop back register the loop register controls the digital loopbacks of the u-transceiver. the analog loopback (no. 3) is closed by c/i= arl. note: if the eoc automatic mode is selected (mfilt.eoc filter = 100), then register loop is accessed by the internal eoc processor: eoc-command lb1 (lb2) sets loop.u/iom and loop.lb1 (loop.lb2) eoc-command rtn resets loop.lb1, loop.lb2 and loop.lbbd loop read* ) / write address: 70 h reset value: 08 h 76543210 0 dlb trans u/iom 1 lbbd lb2 lb1 dlb close framer/deframer loopback C the loopback is closed at the analog/digital interface C prerequisite is that lb1, lb2, lbbd and u/iom ? are set to 0 C only user data is looped and no maintenance data is looped back 1) 0 = framer/deframer loopback open 1 = framer/deframer loopback closed trans transparent/ non-transparent loopback C in transparent mode user data is both passed on and looped back, whereas in non-transparent mode data is not forwarded but substituted by 1s (idle code) and just looped back 2) C if lbbd, lb2, lb1 is closed towards the iom ? interface and bit trans is set to 0 then the state machine has to be put into state transparent first (e.g. by c/i = dt) before data is output on the u-interface C bit trans has no effect on dlb and the analog loopback (arl operates always in transparent mode) 0 = sets transparent loop mode for lbbd, lb2, lb1 1 = sets non-transparent mode for lbbd, lb2, lb1 1s are sent on the iom ? -2/pcm interface in the corresponding time-slot pef 81912/81913 register description data sheet 225 2001-03-30 4.11.15 febe - far end block error counter register the f ar e nd b lock e rror counter register contains the febe value. if the register is read out it is automatically reset to 0. febe read address: 71 h reset value: 00 h u/iom close lbbd, lb2, lb1 towards u or towards iom ? C switch that selects whether loopback lb1, lb2 or lbbd is closed towards u or towards iom ? -2 C the setting affects all test loops, lbbd, lb2 and lb1 C an individual selection for lbbd, lb2, lb1 is not possible 0 = lb1, lb2, lbbd loops are closed from iom ? -2 to iom ? -2 1 = lb1, lb2, lbbd loops are closed from u to u lbbd close complete loop (b1, b2, d) near the system interface the direction towards the loop is closed is determined by bit u/iom 0 = complete loopback open 1 = complete loopback closed lb2 close loop b2 near the system interface the direction towards the loop is closed is determined by bit u/iom 0 = loopback b2 open 1 = loopback b2 closed lb1 close loop b1 near the system interface the direction towards the loop is closed is determined by bit u/iom 0 = loopback b1 open 1 = loopback b1 closed 1) if in state transparent the dlb-loopback is closed from iom- to iom, then c/i-code dc instead of ai is issued on the iom ? -2-interface. 2) if in state transparent the non-transparent lbbd-loopback is closed from u- to u, then c/i-code dc instead of ai is issued on the iom ? -2-interface. however, the correct c/i-code ai can be read from register ucir. 76543210 pef 81912/81913 register description data sheet 226 2001-03-30 4.11.16 nebe - near end block error counter register the n ear e nd b lock e rror counter register contains the nebe value. if the register is read out it is automatically reset to 0. nebe read address: 72 h reset value: 00 h 4.11.17 istau - interrupt status register u-interface the i nterrupt sta tus register u -interface generates an interrupt for the unmasked interrupt flags. refer to chapter 2.4.12 for details on masking and clearing of interrupt flags. for the timing of the interrupt flags istau(3:0) refer to chapter 2.4.2.4 . istau read address: 7a h reset value: 00 h febe counter value 76543210 nebe counter value 76543210 mlt ci febe/ nebe m56 m4 eoc 6ms 12ms mlt mlt interrupt indication 0 = inactive 1 = mlt interrupt has occurred ci c/i code indication the ci interrupt is generated independently on opmode.uci 0 = inactive 1 = ci code change has occurred pef 81912/81913 register description data sheet 227 2001-03-30 4.11.18 masku - mask register u-interface the interrupt mask register u -interface selectively masks each interrupt source in the istau register by setting the corresponding bit to 1. masku read* ) / write address: 7b h reset value: ff h febe/ nebe far end/near end block error indication register m56r notifies whether a febe or nebe has been detected 0 = inactive 1 = febe/nebe occurred m56 validated new m56 bit data received from u-interface 0 = inactive 1 = change of any m5, m6 bit has been detected in receive direction m4 validated new m4 bit data received from u-interface 0 = inactive 1 = change of any m4 bit has been detected in receive direction eoc validated new eoc data received from u-interface 0 = inactive 1 = new eoc message has been received and acknowledged from u 6 ms 6 ms timer for the transmission of eoc commands on u 0 = inactive 1 = indicates when a eoc command is going to be issued on u 12 ms superframe marker (each 12 ms) is going to be issued on u in transmit direction bellcore test requirement: sr-nwt-002397 0 = inactive 1 = indicates when a sf marker is going to be transmitted on u 76543210 pef 81912/81913 register description data sheet 228 2001-03-30 4.11.19 fw_version fw _ v ersion register contains the firmware version number fw _ v ersion read address: 7d h reset value: 6x h version 1.2 : 6d h version 1.3 : 6c h masku value bit 0..7 mask bits 0 = interrupt active 1 = interrupt masked 76543210 firmware version number pef 81912/81913 electrical characteristics data sheet 229 2001-03-30 5 electrical characteristics 5.1 absolute maximum ratings ? esd integrity (according eia/jesd22-a114b (hbm)): 2 kv note: stress above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. line overload protection the q-smint ? ix is compliant to esd tests according to ansi / eos / esd-s 5.1-1993 (cdm), eia/jesd22-a114b (hbm) and to latch-up tests according to jedec eia / jesd78. from these tests the following max. input currents are derived ( table 41 ): ? parameter symbol limit values unit ambient temperature under bias t a -40 to 85 c storage temperature t stg C 65 to 150 c maximum voltage on v dd v dd 4.2 v maximum voltage on any pin with respect to ground v s -0.3 to v dd + 3.3 (max. < 5.5) v table 41 maximum input currents test pulse width current remarks esd 100 ns 1.3 a 3 repetitions latch-up 5 ms +/-200 ma 2 repetitions, respectively dc -- 10 ma pef 81912/81913 electrical characteristics data sheet 230 2001-03-30 5.2 dc characteristics ? table 42 s-transceiver characteristics v dd / v dda = 3.3 v +/- 5% ; v ss / v ssa = 0 v; t a = -40 to 85 c digital pins parameter symbol limit values unit test condition min. max. all input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 5.25 v all except dd/du act ,lp2i mclk output low voltage v ol1 0.45 v i ol1 = 3.0 ma output high voltage v oh1 2.4 v i oh1 = 3.0 ma dd/du act ,lp2i mclk output low voltage v ol2 0.45 v i ol2 = 4.0 ma output high voltage (dd/du push-pull) v oh2 2.4 v i oh2 = 4.0 ma all input leakage current i li 10 a 0 v v in v dd output leakage current i lo 10 a 0 v v in v dd analog pins ain, bin input leakage current i li 70 a 0 v v in v d d pin parameter symbol limit values unit test condition min. typ. max. sx1,2 absolute value of output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.2 2.31 v r l = 50 w sx1,2 s-transmitter output impedance z x 10 34 k w see 1) 1) requirement itu-t i.430, chapter 8.5.1.1a): at all times except when transmitting a binary zero, the output impedance , in the frequency range of 2khz to 1 mhz, shall exceed the impedance indicated by the template in figure 11. the requirement is applicable with an applied sinusoidal voltage of 100 mv (r.m.s value) 0 see 2)3) sr1,2 s-receiver input impedance z r 10 100 k w w v dd = 3.3 v v dd = 0 v pef 81912/81913 electrical characteristics data sheet 231 2001-03-30 table 43 u-transceiver characteristics 2) requirement itu-t i.430, chapter 8.5.1.1b): when transmitting a binary zero, the output impedance shall be > 20 w .: must be met by external circuitry. 3) requirement itu-t i.430, chapter 8.5.1.1b), note: the output impedance limit shall apply for a nominal load impedance (resistive) of 50 w . the output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. the peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. the limitation applies for pulses of both polarities. limit values unit min. typ. max. receive path signal / (noise + total harmonic distortion) 1) 1) test conditions: 1.4 vpp differential sine wave as input on ain/bin with long range (low, critical range). 65 2) 2) versions pef 8x913 with enhanced performance of the u-interface are tested with tightened limit values db dc-level at ad-output 45 50 55 % 3) 3) the percentage of the "1 "-values in the pdm-signal. threshold of level detect (measured between ain and bin with respect to zero signal) 4 5 16 (pef 81912) mv peak 9 (pef 81913) input impedance ain/bin 80 k w transmit path signal / (noise + total harmonic distortion) 4) 4) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 70 db below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. 70 db common mode dc-level 1.61 1.65 1.69 v offset between aout and bout 35 mv absolute peak voltage for a single +3 or -3 pulse measured between aout and bout 5) 5) the signal amplitude measured over a period of 1 min. varies less than 1%. 2.42 2.5 2.58 v output impedance aout/bout: power-up power-down 0.8 3 1.5 6 w w pef 81912/81913 electrical characteristics data sheet 232 2001-03-30 5.3 capacitances t a = 25 c, 3.3 v 5 % v ssa = 0 v, v ssd = 0 v, f c = 1 mhz, unmeasured pins grounded. ? 5.4 power consumption ? 5.5 supply voltages vdd d = + vdd 5% vdd a = + vdd 5% the maximum sinusoidal ripple on vdd is specified in the following figure: table 44 pin capacitances parameter symbol limit values unit remarks min. max. digital pads: input capacitance i/o capacitance c in c i/o 7 7 pf pf analog pads: load capacitance c l 3 pf pin ain, bin power consumption vdd=3.3 v, vss=0 v, inputs at vss/vdd, no led connected, 50% bin. zeros, no output loads except sx1,2 (50 w 1) ) 1) 50 w (2 x tr) on the s-bus. parameter limit values unit test condition min. typ. max. operational u and s enabled, iom ? -2 off 235 200 mw mw u: etsi loop 1 (0 m) u: etsi loop 2.(typical line) power down 15 mw pef 81912/81913 electrical characteristics data sheet 233 2001-03-30 ? figure 83 maximum sinusoidal ripple on supply voltage 5.6 ac characteristics t a = -40 to 85 c, v dd = 3.3 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 84 . ? figure 84 input/output waveform for ac tests parameter all output pins symbol limit values unit min max fall time 30 ns rise time 30 ns 80 100 frequency / khz 10 100 mv (peak) 200 supply voltage ripple frequency ripple itd04269.vsd 60 device under test c load =50 pf 2.4 0.45 2.0 0.8 0.8 2.0 test points its00621.vsd pef 81912/81913 electrical characteristics data sheet 234 2001-03-30 5.6.1 iom ? -2 interface ? figure 85 iom ? -2 interface - bit synchronization timing ? figure 86 iom ? -2 interface - frame synchronization timing t 7 t 18 sds1,2 dcl du/dd (input) t 4 t 5 data valid last bit first bit du/dd (output) t 6 t 8 bit n bit n+1 du/dd (output) iom-timing.vsd fsc dcl t 9 t 10 bcl t 11 t 12 t 13 t 14 t 2 t 3 t 1 pef 81912/81913 electrical characteristics data sheet 235 2001-03-30 ? note: at the start and end of a reset period, a frame jump may occur. this results in a dcl, bcl and fsc high time of min. 130 ns after this specific event. parameter iom ? -2 interface symbol limit values unit min typ max dcl period t 1 565 651 735 ns dcl high t 2 200 310 420 ns dcl low t 3 200 310 420 ns input data setup t 4 20 ns input data hold t 5 20 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 100 ns output data from active to high impedance t 7 100 ns output data delay from clock t 8 80 ns fsc high t 9 50% of fsc cycle time ns fsc advance to dcl t 10 65 130 195 ns bcl high t 11 565 651 735 ns bcl low t 12 565 651 735 ns bcl period t 13 1130 1302 1470 ns fsc advance to bcl t 14 65 130 195 ns dcl, fsc rise/fall t 15 30 ns data out fall (c l = 50 pf, r = 2 k w to v dd , open drain) t 16 200 ns data out rise/fall (c l = 50 pf, tristate) t 17 150 ns strobe signal delay t 18 120 ns pef 81912/81913 electrical characteristics data sheet 236 2001-03-30 5.6.2 serial p interface ? figure 87 serial control interface ? parameter sci interface symbol limit values unit min max sclk cycle time t 1 200 ns sclk high time t 2 80 ns sclk low time t 3 80 ns cs setup time t 4 20 ns cs hold time t 5 10 ns sdr setup time t 6 15 ns sdr hold time t 7 15 ns sdx data out delay t 8 60 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 60 ns cs high to sclk t 11 10 ns sclk sdr cs sdx t 1 t 2 t 3 t 4 t 7 t 10 t 8 t 6 t 9 t 11 t 5 sci_timing.vsd pef 81912/81913 electrical characteristics data sheet 237 2001-03-30 5.6.3 parallel p interface siemens/intel bus mode ? figure 88 microprocessor read cycle ? figure 89 microprocessor write cycle ? figure 90 multiplexed address timing ad0 - ad7 rd x cs data t rr t rd t ri itt00712.vsd t df t dh ad0 - ad7 wr x cs data t ww t dw t wi t wd itt00713.vsd t la wr x cs or rd x cs ad0 - ad7 address t aa t al t als t ad ale itt00714.vsd pef 81912/81913 electrical characteristics data sheet 238 2001-03-30 ? figure 91 non-multiplexed address timing motorola bus mode ? figure 92 microprocessor read timing ? figure 93 microprocessor write cycle t as t ah wr x cs or rd x cs a0 - a6 address itt009661.vsd d0 - d7 cs x ds r/w t rr t rd t ri t rwd t dsd itt00716.vsd data t df t dh d0 - d7 cs x ds data t ww t dw t wi t wd r/w t rwd t dsd itt09679.vsd pef 81912/81913 electrical characteristics data sheet 239 2001-03-30 ? figure 94 non-multiplexed address timing microprocessor interface timing ? parameter symbol limit values unit min. max. ale pulse width t aa 20 ns address setup time to ale t al 10 ns address hold time from ale t la 10 ns address latch setup time to wr , rd t als 10 ns address setup time t as 10 ns address hold time t ah 10 ns ale guard time t ad 10 ns ds delay after r/w setup t dsd 10 ns rd pulse width t rr 80 ns data output delay from rd t rd 80 ns data hold from rd t dh 0ns data float from rd t df 25 ns rd control interval 1) t ri 70 ns w pulse width t ww 60 ns data setup time to w x cs t dw 10 ns data hold time w x cs t wd 10 ns w control interval t wi 70 ns r/w hold from cs x ds inactive t rwd 10 ns t as t ah a0 - a6 cs x ds itt09662.vsd address pef 81912/81913 electrical characteristics data sheet 240 2001-03-30 5.6.4 reset table 45 reset input signal characteristics ? figure 95 reset input signal 1) control interval: t ri ' is minimal 70ns for all registers except istau, febe and nebe. however, the time between two consecutive read accesses to one of the registers istau, febe or nebe, respectively, must be longer than 330ns. this does not limit t ri of read sequences, which involve intermediate read access to other registers, as for instance: istau -(t ri )- ista -(t ri )- istah -(t ri )- istau. parameter symbol limit values unit test conditions min. typ. max. length of active low state t rst 4 ms power on the 4 ms are assumed to be long enough for the oscillator to run correctly 2 x dcl clock cycles + 400 ns after power on delay time for m c access after rst rising edge t m c 500 ns t rst rst itd09823.vsd t m c pef 81912/81913 electrical characteristics data sheet 241 2001-03-30 5.6.5 undervoltage detection characteristics ? figure 96 undervoltage control timing table 46 parameters of the uvd/por circuit v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. detection threshold 1) v det 2.7 2.8 2.92 v v dd = 3.3 v 5 % hysteresis v hys 30 90 mv max. rising/falling v dd edge for activation/ deactivation of uvd dv dd /dt 0.1 v/s max. rising v dd for power-on 2) 0.1 v/ ms min. operating voltage v ddmin 1.5 v v dd v ddmin v det t t rsto t act t act t deact t deact v hys vdddet.vsd pef 81912/81913 electrical characteristics data sheet 242 2001-03-30 delay for activation of rsto t act 10 s delay for deactivation of rsto t deact 64 ms 1) the detection threshold v det is far below the specified supply voltage range of analog and digital parts of the q-smint ? ix. therefore, the board designer must take into account that a range of voltages is existing, where neither performance and functionality of the q-smint ? ix are guaranteed, nor a reset is generated. 2) if the integrated power-on reset of the q-smintix is selected (vdddet = 0) and the supply voltage v dd is ramped up from 0v to 3.3v +/- 5%, then the q-smintix is kept in reset during v ddmin < v dd < v det + v hys . v dd must be ramped up so slowly that the q-smintix leaves the reset state after the oscillator circuit has already finished start-up. the start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. pef 81912/81913 package outlines data sheet 243 2001-03-30 6 package outlines ? plastic package, p-mqfp-64 (metric quad flat package) pef 81912/81913 package outlines data sheet 244 2001-03-30 ? plastic package, p-tqfp-64 (thin quad flat package) pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 245 2001-03-30 7 appendix: differences between q- and t-smint ? ix the q- and t-smint ? ix have been designed to be as compatible as possible. however, some differences between them are unavoidable due to the different line codes 2b1q and 4b3t used for data transmission on the u k0 line. especially the pin compatibility between q- and t-smint ? ix allows for one single pcb design for both series with only some mounting differences. the m c software can distinguish between the q- and t-series by reading the identification register via the iom ? -2 (monitor channel identification command) or the m c interface (register id.design), respectively. the following chapter summarizes the main differences between the q- and t- smint ? ix. 7.1 pinning ? table 47 pin definitions and functions pin t/mqfp-64 q-smint ? ix: 2b1q t-smint ? ix: 4b3t 16 metallic termination input (mti) tie to 1 55 power status (primary) (ps1) tie to 1 41 power status (secondary) (ps2) tie to 1 pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 246 2001-03-30 7.2 u-transceiver 7.2.1 u-interface conformity ? table 48 related documents to the u-interface q-smint ? ix: 2b1q t-smint ? ix: 4b3t etsi: ts 102 080 conform to annex a compliant to 10 ms interruptions conform to annex b ansi: t1.601-1998 (revision of ansi t1.601- 1992) conform mlt input and decode logic not required cnet: st/laa/elr/dnp/ 822 conform not required rc7355e conform not required ftz-richtlinie 1 tr 220 not required conform pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 247 2001-03-30 7.2.2 u-transceiver state machines ? figure 97 intc-q compatible state machine q-smint ? ix: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e&di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 248 2001-03-30 ? figure 98 simplified state machine q-smint ? ix: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al ar ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd lof t1s, t11s ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e & di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s tim pu pu pu pu pu or tim or tim dr t7e&tim dr dr dr t1s t11s pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 249 2001-03-30 ? figure 99 iec-t/ntc-t compatible state machine t-smint ? ix: 4b3t both the q- and the t-smint ? ix u-transceiver can be controlled via state machines, which are compatible to those defined for the old nt generation intc-q and ntc-t. additionally, the q-smint ? ix possesses a newly defined, so called simplified state machine. this simplified state machine can be used optionally instead of the intc-q compatible state machine and eases the u-transceiver control by software. such a simplified state machine is not available for the t-smint ? ix. awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 synchronizing rsy (u0&t12e) u2 t12s t13e u1a ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai/ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0 pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 250 2001-03-30 7.2.3 command/indication codes table 49 c/i codes code q-smint ? ix: 2b1q t-smint ? ix: 4b3t in out in out 0000 tim dr tim dr 0001 res C C C 0010 C C C C 0011 C C C C 0100 ei1 ei1 C rsy 0101 ssp C ssp C 0110 dt C dt C 0111 C pu C C 1000 ar ar ar ar 1001 C C C C 1010 arl arl C arl 1011 C C C C 1100 ai ai ai ai 1101 C C res C 1110 C ail C ail 1111 di dc di dc pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 251 2001-03-30 7.2.4 interrupt structure ? figure 100 interrupt structure u-transceiver q-smint ? ix: 2b1q a1 a2 i8 aib uoa m46 m45 m44 sco dea act mlt ci febe/ nebe m56 m4 eoc 6ms 12ms mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 0 ms2 ms1 nebe m61 m52 m51 febe m56r m4r m4rmask mfilt opmode.mlt crc, tll, no filtering tll, chg, no filtering mfilt eocr istau masku 0 7 0 7 0 7 crc, tll, no filtering 15 0 11 + mfilt + reserved interr_u_q2.vsd u ista mask int ucir 0 7 c/i c/i c/i c/i 0 7 pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 252 2001-03-30 ? figure 101 interrupt structure u-transceiver t-smint ? ix: 4b3t u s ... ... ... ... ... ... ista mask int intstruct_4b3t.emf 0 ci 0 0 1ms 1 ci 1 1 1ms 0 7 ucir 0 7 0 0 0 0 c/i c/i c/i c/i rds rds 0 0 1 1 istau masku pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 253 2001-03-30 7.2.5 register summary u-transceiver u-interface registers q-smint ? ix: 2b1q name 7 6 5 4 3 2 1 0 addr r/w res opmode 0 uci febe mlt 0 ci_ sel 0060 h r*/w 14 h mfilt m56 filter m4 filter eoc filter 61 h r*/w 14 h reserved 62 h eocr 0 0 0 0 a1 a2 a3 d/m 63 h r0f i1 i2 i3 i4 i5 i6 i7 i8 64 h ff h eocw 0 0 0 0 a1 a2 a3 d/m 65 h w01 h i1 i2 i3 i4 i5 i6 i7 i8 66 h 00 h m4rmask m4 read mask bits 67 h r*/w 00 h m4wmask m4 write mask bits 68 h r*/w a8 h m4r verified m4 bit data of last received superframe 69 h rbe h m4w m4 bit data to be send with next superframe 6a h r*/w be h m56r 0 ms2 ms1 nebe m61 m52 m51 febe 6b h r1f h m56w 1 1 1 1 m61 m52 m51 febe 6c h wff h ucir 0 0 0 0 c/i code output 6d h r00 h uciw 0 0 0 0 c/i code input 6e h w01 h test 0 0 0 0 ccrc +-1 tones 040khz6f h r*/w 00 h loop 0 dlb trans u/iom ? 1lbbdlb2lb170 h r*/w 08 h febe febe counter value 71 h r00 h nebe nebe counter value 72 h r00 h reserved 73 h - 79 h pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 254 2001-03-30 istau mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7a h r00 h masku mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r6x h reserved 7e h - 7f h name 7 6 5 4 3 2 1 0 addr r/w res pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 255 2001-03-30 u-interface registers t-smint ? ix: 4b3t name 7 6 5 4 3 2 1 0 addr r/w res opmode 0 uci 0 0 0 0 0 060 h r*/w 00 h reserved 61 h - 6c h ucir 0 0 0 0 c/i code output 6d h r00 h uciw 0 0 0 0 c/i code input 6e h w01 h reserved 6f h loop 0 dlb transu/iom ? 1lbbdlb2lb170 h r*/w 08 h reserved 71 h rds block error counter value 72 h r00 h reserved 73 h - 79 h istau 0 ci rds 0 0 0 0 1 ms 7a h r00 h masku 1 ci rds 1 1 1 1 1 ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r3x h reserved 7e h - 7f h pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 256 2001-03-30 7.3 external circuitry the external circuitry of the q- and t-smint ? ix is equivalent; however, some external components of the u-transceiver hybrid must be dimensioned different for 2b1q and 4b3t. all information on the external circuitry is preliminary and may be changed in future documents. ? figure 102 external circuitry q- and t-smint ? ix note: the necessary protection circuitry is not displayed in figure 102 . loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 81912/81913 appendix: differences between q- and t-smint?ix data sheet 257 2001-03-30 table 50 dimensions of external components component q-smint ? ix: 2b1q t-smint ? ix: 4b3t transformer: ratio main inductivity 1:2 14.5 mh 1:1.6 7.5 mh resistance r3 1.3 k w 1.75 k w resistance r4 1.0 k w 1.0 k w resistance r t 9.5 w 25 w capacitor c 27 nf 15 nf r ptc and r comp 2r ptc + 8r comp = 40 w n 2 (2r comp + r b ) + r l = 20 w pef 81912/81913 index data sheet 258 2001-03-30 8 index a absolute maximum ratings 229 address space 155 b block diagram 7 block error counters 80 c c/i channel detailed registers 168 functional description 50 c/i codes s-transceiver 108 u-transceiver 82 controller data access (cda) 31 cyclic redundancy check 78 d dc characteristics 230 d-channel access control functional description 51 state machine 55 differences between q- and t-smint 245 e eoc 66 external circuitry s-transceiver 151 u-transceiver 149 f features 3 h hdlc controller data reception 120 data transmission 128 detailed registers 168 functional description 119 message transfer modes 119 i identification via monitor channel 48 via register access 198 interrupts 156 iom?-2 interface ac characteristics 234 activation/deactivation 58 detailed registers 199 frame structure 28 functional description 28 l layer 1 activation/deactivation 139 loopbacks 144 led pins 13 line overload protection 229 m maintenance channel 63 metallic loop termination 98 microcontroller clock generation 24 microcontroller interfaces interface selection 17 parallel microcontroller interface 22 serial control interface (sci) 18 monitor channel detailed registers 211 error treatment 46 functional description 42 handshake procedure 42 interrupt logic 49 time-out procedure 49 o oscillator circuitry 153 overhead bits 74 p package outlines 243 pef 81912/81913 index data sheet 259 2001-03-30 parallel microcontroller interface ac-characteristics 237 functional description 22 pin configuration 6 pin definitions and functions 8 power consumption 232 power supply blocking 149 power-on reset 27, 241 r register summary 158 reset generation 25 input signal characteristics 240 power-on reset 27, 241 under voltage detection 27, 241 s s/q channels 104 scrambling/ descrambling 82 serial control interface (sci) ac-characteristics 236 functional description 18 serial data strobe signal 41 stop/go bit handling 53 s-transceiver detailed registers 186 functional description 102 state machine, lt-s 114 state machine, nt 110 supply voltages 232 synchronous transfer 37 system integration 14 t test modes 14 tic bus handling 52 u u-interface hybrid 149 under voltage detection 27, 241 u-transceiver detailed registers 214 functional description 60 state machine, simplified nt 94 state machine, standard nt 86 w watchdog timer 26 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. dr. ulrich schumacher |
Price & Availability of PEF81912
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |